?? topclock.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "setm register minute1:u2\|comb~1 register minute1:u2\|comb~6 249.94 MHz 4.001 ns Internal " "Info: Clock \"setm\" has Internal fmax of 249.94 MHz between source register \"minute1:u2\|comb~1\" and destination register \"minute1:u2\|comb~6\" (period= 4.001 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.740 ns + Longest register register " "Info: + Longest register to register delay is 3.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute1:u2\|comb~1 1 REG LC_X13_Y14_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y14_N9; Fanout = 5; REG Node = 'minute1:u2\|comb~1'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { minute1:u2|comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.423 ns) 1.150 ns minute1:u2\|Add0~132 2 COMB LC_X12_Y14_N0 3 " "Info: 2: + IC(0.727 ns) + CELL(0.423 ns) = 1.150 ns; Loc. = LC_X12_Y14_N0; Fanout = 3; COMB Node = 'minute1:u2\|Add0~132'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.150 ns" { minute1:u2|comb~1 minute1:u2|Add0~132 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.228 ns minute1:u2\|Add0~124 3 COMB LC_X12_Y14_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.228 ns; Loc. = LC_X12_Y14_N1; Fanout = 2; COMB Node = 'minute1:u2\|Add0~124'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { minute1:u2|Add0~132 minute1:u2|Add0~124 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.306 ns minute1:u2\|Add0~118 4 COMB LC_X12_Y14_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.306 ns; Loc. = LC_X12_Y14_N2; Fanout = 2; COMB Node = 'minute1:u2\|Add0~118'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { minute1:u2|Add0~124 minute1:u2|Add0~118 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.384 ns minute1:u2\|Add0~126 5 COMB LC_X12_Y14_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.384 ns; Loc. = LC_X12_Y14_N3; Fanout = 2; COMB Node = 'minute1:u2\|Add0~126'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { minute1:u2|Add0~118 minute1:u2|Add0~126 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.562 ns minute1:u2\|Add0~128 6 COMB LC_X12_Y14_N4 5 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.562 ns; Loc. = LC_X12_Y14_N4; Fanout = 5; COMB Node = 'minute1:u2\|Add0~128'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { minute1:u2|Add0~126 minute1:u2|Add0~128 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.183 ns minute1:u2\|Add0~129 7 COMB LC_X12_Y14_N5 2 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.183 ns; Loc. = LC_X12_Y14_N5; Fanout = 2; COMB Node = 'minute1:u2\|Add0~129'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.621 ns" { minute1:u2|Add0~128 minute1:u2|Add0~129 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.292 ns) 3.177 ns minute1:u2\|m~179 8 COMB LC_X13_Y14_N7 1 " "Info: 8: + IC(0.702 ns) + CELL(0.292 ns) = 3.177 ns; Loc. = LC_X13_Y14_N7; Fanout = 1; COMB Node = 'minute1:u2\|m~179'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.994 ns" { minute1:u2|Add0~129 minute1:u2|m~179 } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.115 ns) 3.740 ns minute1:u2\|comb~6 9 REG LC_X13_Y14_N8 4 " "Info: 9: + IC(0.448 ns) + CELL(0.115 ns) = 3.740 ns; Loc. = LC_X13_Y14_N8; Fanout = 4; REG Node = 'minute1:u2\|comb~6'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.563 ns" { minute1:u2|m~179 minute1:u2|comb~6 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.863 ns ( 49.81 % ) " "Info: Total cell delay = 1.863 ns ( 49.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.877 ns ( 50.19 % ) " "Info: Total interconnect delay = 1.877 ns ( 50.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.740 ns" { minute1:u2|comb~1 minute1:u2|Add0~132 minute1:u2|Add0~124 minute1:u2|Add0~118 minute1:u2|Add0~126 minute1:u2|Add0~128 minute1:u2|Add0~129 minute1:u2|m~179 minute1:u2|comb~6 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.740 ns" { minute1:u2|comb~1 minute1:u2|Add0~132 minute1:u2|Add0~124 minute1:u2|Add0~118 minute1:u2|Add0~126 minute1:u2|Add0~128 minute1:u2|Add0~129 minute1:u2|m~179 minute1:u2|comb~6 } { 0.000ns 0.727ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.702ns 0.448ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.115ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "setm destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"setm\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setm 1 CLK PIN_28 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 16; CLK Node = 'setm'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { setm } "NODE_NAME" } } { "topclock.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns minute1:u2\|comb~6 2 REG LC_X13_Y14_N8 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y14_N8; Fanout = 4; REG Node = 'minute1:u2\|comb~6'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { setm minute1:u2|comb~6 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { setm minute1:u2|comb~6 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { setm setm~out0 minute1:u2|comb~6 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "setm source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"setm\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns setm 1 CLK PIN_28 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 16; CLK Node = 'setm'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { setm } "NODE_NAME" } } { "topclock.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns minute1:u2\|comb~1 2 REG LC_X13_Y14_N9 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X13_Y14_N9; Fanout = 5; REG Node = 'minute1:u2\|comb~1'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { setm minute1:u2|comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { setm minute1:u2|comb~1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { setm setm~out0 minute1:u2|comb~1 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { setm minute1:u2|comb~6 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { setm setm~out0 minute1:u2|comb~6 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { setm minute1:u2|comb~1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { setm setm~out0 minute1:u2|comb~1 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.740 ns" { minute1:u2|comb~1 minute1:u2|Add0~132 minute1:u2|Add0~124 minute1:u2|Add0~118 minute1:u2|Add0~126 minute1:u2|Add0~128 minute1:u2|Add0~129 minute1:u2|m~179 minute1:u2|comb~6 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.740 ns" { minute1:u2|comb~1 minute1:u2|Add0~132 minute1:u2|Add0~124 minute1:u2|Add0~118 minute1:u2|Add0~126 minute1:u2|Add0~128 minute1:u2|Add0~129 minute1:u2|m~179 minute1:u2|comb~6 } { 0.000ns 0.727ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.702ns 0.448ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.115ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { setm minute1:u2|comb~6 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { setm setm~out0 minute1:u2|comb~6 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { setm minute1:u2|comb~1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { setm setm~out0 minute1:u2|comb~1 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "seth register hour1:u3\|comb~1 register hour1:u3\|comb~4 270.34 MHz 3.699 ns Internal " "Info: Clock \"seth\" has Internal fmax of 270.34 MHz between source register \"hour1:u3\|comb~1\" and destination register \"hour1:u3\|comb~4\" (period= 3.699 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.438 ns + Longest register register " "Info: + Longest register to register delay is 3.438 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour1:u3\|comb~1 1 REG LC_X25_Y10_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y10_N9; Fanout = 5; REG Node = 'hour1:u3\|comb~1'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { hour1:u3|comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.432 ns) 1.168 ns hour1:u3\|Add0~118COUT1_134 2 COMB LC_X24_Y10_N0 3 " "Info: 2: + IC(0.736 ns) + CELL(0.432 ns) = 1.168 ns; Loc. = LC_X24_Y10_N0; Fanout = 3; COMB Node = 'hour1:u3\|Add0~118COUT1_134'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.168 ns" { hour1:u3|comb~1 hour1:u3|Add0~118COUT1_134 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.248 ns hour1:u3\|Add0~120COUT1_135 3 COMB LC_X24_Y10_N1 3 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.248 ns; Loc. = LC_X24_Y10_N1; Fanout = 3; COMB Node = 'hour1:u3\|Add0~120COUT1_135'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { hour1:u3|Add0~118COUT1_134 hour1:u3|Add0~120COUT1_135 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.328 ns hour1:u3\|Add0~122COUT1_136 4 COMB LC_X24_Y10_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.328 ns; Loc. = LC_X24_Y10_N2; Fanout = 2; COMB Node = 'hour1:u3\|Add0~122COUT1_136'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { hour1:u3|Add0~120COUT1_135 hour1:u3|Add0~122COUT1_136 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 1.936 ns hour1:u3\|Add0~123 5 COMB LC_X24_Y10_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.608 ns) = 1.936 ns; Loc. = LC_X24_Y10_N3; Fanout = 2; COMB Node = 'hour1:u3\|Add0~123'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.608 ns" { hour1:u3|Add0~122COUT1_136 hour1:u3|Add0~123 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.292 ns) 2.947 ns hour1:u3\|h~108 6 COMB LC_X25_Y10_N3 1 " "Info: 6: + IC(0.719 ns) + CELL(0.292 ns) = 2.947 ns; Loc. = LC_X25_Y10_N3; Fanout = 1; COMB Node = 'hour1:u3\|h~108'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.011 ns" { hour1:u3|Add0~123 hour1:u3|h~108 } "NODE_NAME" } } { "hour1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/hour1.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 3.438 ns hour1:u3\|comb~4 7 REG LC_X25_Y10_N4 4 " "Info: 7: + IC(0.182 ns) + CELL(0.309 ns) = 3.438 ns; Loc. = LC_X25_Y10_N4; Fanout = 4; REG Node = 'hour1:u3\|comb~4'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.491 ns" { hour1:u3|h~108 hour1:u3|comb~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.801 ns ( 52.39 % ) " "Info: Total cell delay = 1.801 ns ( 52.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.637 ns ( 47.61 % ) " "Info: Total interconnect delay = 1.637 ns ( 47.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.438 ns" { hour1:u3|comb~1 hour1:u3|Add0~118COUT1_134 hour1:u3|Add0~120COUT1_135 hour1:u3|Add0~122COUT1_136 hour1:u3|Add0~123 hour1:u3|h~108 hour1:u3|comb~4 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.438 ns" { hour1:u3|comb~1 hour1:u3|Add0~118COUT1_134 hour1:u3|Add0~120COUT1_135 hour1:u3|Add0~122COUT1_136 hour1:u3|Add0~123 hour1:u3|h~108 hour1:u3|comb~4 } { 0.000ns 0.736ns 0.000ns 0.000ns 0.000ns 0.719ns 0.182ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.608ns 0.292ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "seth destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"seth\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns seth 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'seth'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { seth } "NODE_NAME" } } { "topclock.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns hour1:u3\|comb~4 2 REG LC_X25_Y10_N4 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X25_Y10_N4; Fanout = 4; REG Node = 'hour1:u3\|comb~4'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { seth hour1:u3|comb~4 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { seth hour1:u3|comb~4 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { seth seth~out0 hour1:u3|comb~4 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "seth source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"seth\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns seth 1 CLK PIN_29 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 16; CLK Node = 'seth'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { seth } "NODE_NAME" } } { "topclock.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns hour1:u3\|comb~1 2 REG LC_X25_Y10_N9 5 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X25_Y10_N9; Fanout = 5; REG Node = 'hour1:u3\|comb~1'" { } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { seth hour1:u3|comb~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { seth hour1:u3|comb~1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { seth seth~out0 hour1:u3|comb~1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { seth hour1:u3|comb~4 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { seth seth~out0 hour1:u3|comb~4 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { seth hour1:u3|comb~1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { seth seth~out0 hour1:u3|comb~1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.438 ns" { hour1:u3|comb~1 hour1:u3|Add0~118COUT1_134 hour1:u3|Add0~120COUT1_135 hour1:u3|Add0~122COUT1_136 hour1:u3|Add0~123 hour1:u3|h~108 hour1:u3|comb~4 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.438 ns" { hour1:u3|comb~1 hour1:u3|Add0~118COUT1_134 hour1:u3|Add0~120COUT1_135 hour1:u3|Add0~122COUT1_136 hour1:u3|Add0~123 hour1:u3|h~108 hour1:u3|comb~4 } { 0.000ns 0.736ns 0.000ns 0.000ns 0.000ns 0.719ns 0.182ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.608ns 0.292ns 0.309ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { seth hour1:u3|comb~4 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { seth seth~out0 hour1:u3|comb~4 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { seth hour1:u3|comb~1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { seth seth~out0 hour1:u3|comb~1 } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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