{ "Info" "ITDB_FULL_TPD_RESULT" "reset Alarm 9.561 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"Alarm\" is 9.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_29 30 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 30; PIN Node = 'reset'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.999 ns) + CELL(0.292 ns) 3.760 ns alarm1:u5\|Alarm~50 2 COMB LC_X15_Y12_N2 1 " "Info: 2: + IC(1.999 ns) + CELL(0.292 ns) = 3.760 ns; Loc. = LC_X15_Y12_N2; Fanout = 1; COMB Node = 'alarm1:u5\|Alarm~50'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.291 ns" { reset alarm1:u5|Alarm~50 } "NODE_NAME" } } { "alarm1.vhd" "" { Text "I:/topclock/alarm1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.677 ns) + CELL(2.124 ns) 9.561 ns Alarm 3 PIN PIN_178 0 " "Info: 3: + IC(3.677 ns) + CELL(2.124 ns) = 9.561 ns; Loc. = PIN_178; Fanout = 0; PIN Node = 'Alarm'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.801 ns" { alarm1:u5|Alarm~50 Alarm } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.885 ns ( 40.63 % ) " "Info: Total cell delay = 3.885 ns ( 40.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.676 ns ( 59.37 % ) " "Info: Total interconnect delay = 5.676 ns ( 59.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "9.561 ns" { reset alarm1:u5|Alarm~50 Alarm } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "9.561 ns" { reset {} reset~out0 {} alarm1:u5|Alarm~50 {} Alarm {} } { 0.000ns 0.000ns 1.999ns 3.677ns } { 0.000ns 1.469ns 0.292ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "hour1:u3\|Enhour reset clk 12.595 ns register " "Info: th for register \"hour1:u3\|Enhour\" (data pin = \"reset\", clock pin = \"clk\") is 12.595 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 17.824 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 17.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.561 ns) + CELL(0.935 ns) 7.965 ns second1:u1\|Ensec 2 REG LC_X8_Y10_N1 9 " "Info: 2: + IC(5.561 ns) + CELL(0.935 ns) = 7.965 ns; Loc. = LC_X8_Y10_N1; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.496 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "I:/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(0.935 ns) 12.412 ns minute1:u2\|Enmin 3 REG LC_X15_Y12_N5 9 " "Info: 3: + IC(3.512 ns) + CELL(0.935 ns) = 12.412 ns; Loc. = LC_X15_Y12_N5; Fanout = 9; REG Node = 'minute1:u2\|Enmin'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.447 ns" { second1:u1|Ensec minute1:u2|Enmin } "NODE_NAME" } } { "minute1.vhd" "" { Text "I:/topclock/minute1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.701 ns) + CELL(0.711 ns) 17.824 ns hour1:u3\|Enhour 4 REG LC_X15_Y14_N9 3 " "Info: 4: + IC(4.701 ns) + CELL(0.711 ns) = 17.824 ns; Loc. = LC_X15_Y14_N9; Fanout = 3; REG Node = 'hour1:u3\|Enhour'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.412 ns" { minute1:u2|Enmin hour1:u3|Enhour } "NODE_NAME" } } { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 22.72 % ) " "Info: Total cell delay = 4.050 ns ( 22.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.774 ns ( 77.28 % ) " "Info: Total interconnect delay = 13.774 ns ( 77.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "17.824 ns" { clk second1:u1|Ensec minute1:u2|Enmin hour1:u3|Enhour } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "17.824 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|Enmin {} hour1:u3|Enhour {} } { 0.000ns 0.000ns 5.561ns 3.512ns 4.701ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.244 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.244 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_29 30 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 30; PIN Node = 'reset'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "topclock.vhd" "" { Text "I:/topclock/topclock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.114 ns) 2.463 ns hour1:u3\|Enhour~12 2 COMB LC_X8_Y10_N6 3 " "Info: 2: + IC(0.880 ns) + CELL(0.114 ns) = 2.463 ns; Loc. = LC_X8_Y10_N6; Fanout = 3; COMB Node = 'hour1:u3\|Enhour~12'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.994 ns" { reset hour1:u3|Enhour~12 } "NODE_NAME" } } { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.914 ns) + CELL(0.867 ns) 5.244 ns hour1:u3\|Enhour 3 REG LC_X15_Y14_N9 3 " "Info: 3: + IC(1.914 ns) + CELL(0.867 ns) = 5.244 ns; Loc. = LC_X15_Y14_N9; Fanout = 3; REG Node = 'hour1:u3\|Enhour'" {  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.781 ns" { hour1:u3|Enhour~12 hour1:u3|Enhour } "NODE_NAME" } } { "hour1.vhd" "" { Text "I:/topclock/hour1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.450 ns ( 46.72 % ) " "Info: Total cell delay = 2.450 ns ( 46.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.794 ns ( 53.28 % ) " "Info: Total interconnect delay = 2.794 ns ( 53.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.244 ns" { reset hour1:u3|Enhour~12 hour1:u3|Enhour } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.244 ns" { reset {} reset~out0 {} hour1:u3|Enhour~12 {} hour1:u3|Enhour {} } { 0.000ns 0.000ns 0.880ns 1.914ns } { 0.000ns 1.469ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "17.824 ns" { clk second1:u1|Ensec minute1:u2|Enmin hour1:u3|Enhour } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "17.824 ns" { clk {} clk~out0 {} second1:u1|Ensec {} minute1:u2|Enmin {} hour1:u3|Enhour {} } { 0.000ns 0.000ns 5.561ns 3.512ns 4.701ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.244 ns" { reset hour1:u3|Enhour~12 hour1:u3|Enhour } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "5.244 ns" { reset {} reset~out0 {} hour1:u3|Enhour~12 {} hour1:u3|Enhour {} } { 0.000ns 0.000ns 0.880ns 1.914ns } { 0.000ns 1.469ns 0.114ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 08 17:00:35 2008 " "Info: Processing ended: Sun Jun 08 17:00:35 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:04 " "Info: Elapsed time: 00:01:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}