library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity specified_temp is		
	port( rise:in std_logic; -----增加溫度的脈沖輸入  起始溫度為30℃，一次增加1℃  最大溫度為45℃
          down:in std_logic;-------減小溫度的脈沖輸入  一次減小1℃
   		  set:in std_logic;--------整數部分或小數部分選擇：set=1為整數，set=10為小數
		  specified_temp:out std_logic_vector(9 downto 0)-----設定溫度輸出10位二進制數
		 );
end specified_temp;
architecture behav of specified_temp is
	signal num:std_logic_vector(3 downto 0);---------總的占空比
	signal num_rise:std_logic_vector(3 downto 0);----rise脈沖計數
	signal num_down:std_logic_vector(3 downto 0);----down脈沖計數
	signal temp:std_logic_vector(9 downto 0);
begin
process(rise)-----增加溫度		
begin
	if (rise'event and rise='1') then 
		if (num="0000") then num_rise<=num_rise+'1';
		elsif (num="1111") then num_rise<=num_rise;		
		else num_rise<=num_rise+1;
		end if;
	end if;
end process;
-------------------減小溫度
process(down)
begin
	if (down'event and down='1') then 
		if (num="0000") then num_down<=num_down;
		elsif (num="1111") then num_down<=num_down+1; 
		else num_down<=num_down+1;
		end if;
    end if;
end process;
num<=num_rise-num_down;
---------------------------
process(set, num)
begin
	if set='1' then temp(9 downto 4)<="011110"+num;
	else temp(3 downto 0)<=num;
	end if;
end process;
------------------------
specified_temp<=temp;
end behav;