{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 30 10:54:21 2007 " "Info: Processing started: Wed May 30 10:54:21 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Hyperthermia_top -c Hyperthermia_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Hyperthermia_top -c Hyperthermia_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "debounce.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file debounce.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 debounce " "Info: Found entity 1: debounce" {  } { { "debounce.bdf" "" { Schematic "D:/my_eda4/Hyperthermia_1/debounce.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Hyperthermia_top.bdf 1 1 " "Warning: Using design file Hyperthermia_top.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Hyperthermia_top " "Info: Found entity 1: Hyperthermia_top" {  } { { "Hyperthermia_top.bdf" "" { Schematic "D:/my_eda4/Hyperthermia_1/Hyperthermia_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Hyperthermia_top " "Info: Elaborating entity \"Hyperthermia_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "display.bdf 1 1 " "Warning: Using design file display.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.bdf" "" { Schematic "D:/my_eda4/Hyperthermia_1/display.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst4 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst4\"" {  } { { "Hyperthermia_top.bdf" "inst4" { Schematic "D:/my_eda4/Hyperthermia_1/Hyperthermia_top.bdf" { { 224 -120 128 352 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "two_to_ten.vhd 2 1 " "Warning: Using design file two_to_ten.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 two_to_ten-behav " "Info: Found design unit 1: two_to_ten-behav" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 two_to_ten " "Info: Found entity 1: two_to_ten" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "two_to_ten display:inst4\|two_to_ten:inst " "Info: Elaborating entity \"two_to_ten\" for hierarchy \"display:inst4\|two_to_ten:inst\"" {  } { { "display.bdf" "inst" { Schematic "D:/my_eda4/Hyperthermia_1/display.bdf" { { 224 136 360 352 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "specified_temp two_to_ten.vhd(24) " "Warning (10492): VHDL Process Statement warning at two_to_ten.vhd(24): signal \"specified_temp\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp two_to_ten.vhd(25) " "Warning (10492): VHDL Process Statement warning at two_to_ten.vhd(25): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "t two_to_ten.vhd(27) " "Warning (10492): VHDL Process Statement warning at two_to_ten.vhd(27): signal \"t\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "t two_to_ten.vhd(28) " "Warning (10492): VHDL Process Statement warning at two_to_ten.vhd(28): signal \"t\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "inte_one two_to_ten.vhd(21) " "Warning (10631): VHDL Process Statement warning at two_to_ten.vhd(21): inferring latch(es) for signal or variable \"inte_one\", which holds its previous value in one or more paths through the process" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 21 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "inte_one\[0\] two_to_ten.vhd(21) " "Info (10041): Verilog HDL or VHDL info at two_to_ten.vhd(21): inferred latch for \"inte_one\[0\]\"" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "inte_one\[1\] two_to_ten.vhd(21) " "Info (10041): Verilog HDL or VHDL info at two_to_ten.vhd(21): inferred latch for \"inte_one\[1\]\"" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "inte_one\[2\] two_to_ten.vhd(21) " "Info (10041): Verilog HDL or VHDL info at two_to_ten.vhd(21): inferred latch for \"inte_one\[2\]\"" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "inte_one\[3\] two_to_ten.vhd(21) " "Info (10041): Verilog HDL or VHDL info at two_to_ten.vhd(21): inferred latch for \"inte_one\[3\]\"" {  } { { "two_to_ten.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/two_to_ten.vhd" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "seven.vhd 2 1 " "Warning: Using design file seven.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seven-one " "Info: Found design unit 1: seven-one" {  } { { "seven.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/seven.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 seven " "Info: Found entity 1: seven" {  } { { "seven.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/seven.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seven display:inst4\|seven:inst4 " "Info: Elaborating entity \"seven\" for hierarchy \"display:inst4\|seven:inst4\"" {  } { { "display.bdf" "inst4" { Schematic "D:/my_eda4/Hyperthermia_1/display.bdf" { { 384 424 544 456 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sepcified_temp_top.bdf 1 1 " "Warning: Using design file sepcified_temp_top.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sepcified_temp_top " "Info: Found entity 1: sepcified_temp_top" {  } { { "sepcified_temp_top.bdf" "" { Schematic "D:/my_eda4/Hyperthermia_1/sepcified_temp_top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sepcified_temp_top sepcified_temp_top:inst2 " "Info: Elaborating entity \"sepcified_temp_top\" for hierarchy \"sepcified_temp_top:inst2\"" {  } { { "Hyperthermia_top.bdf" "inst2" { Schematic "D:/my_eda4/Hyperthermia_1/Hyperthermia_top.bdf" { { 224 -392 -184 336 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "specified_temp.vhd 2 1 " "Warning: Using design file specified_temp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 specified_temp-behav " "Info: Found design unit 1: specified_temp-behav" {  } { { "specified_temp.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/specified_temp.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 specified_temp " "Info: Found entity 1: specified_temp" {  } { { "specified_temp.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/specified_temp.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "specified_temp sepcified_temp_top:inst2\|specified_temp:inst " "Info: Elaborating entity \"specified_temp\" for hierarchy \"sepcified_temp_top:inst2\|specified_temp:inst\"" {  } { { "sepcified_temp_top.bdf" "inst" { Schematic "D:/my_eda4/Hyperthermia_1/sepcified_temp_top.bdf" { { 136 344 520 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "temp specified_temp.vhd(38) " "Warning (10631): VHDL Process Statement warning at specified_temp.vhd(38): inferring latch(es) for signal or variable \"temp\", which holds its previous value in one or more paths through the process" {  } { { "specified_temp.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/specified_temp.vhd" 38 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "temp\[0\] specified_temp.vhd(38) " "Info (10041): Verilog HDL or VHDL info at specified_temp.vhd(38): inferred latch for \"temp\[0\]\"" {  } { { "specified_temp.vhd" "" { Text "D:/my_eda4/Hyperthermia_1/specified_temp.vhd" 38 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}