?? clk_1hz.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_1hz is
port(
clk10k:in std_logic; ------時鐘信號10khZ
clk1hz:out std_logic); -----頻率信號輸出1Hz
end;
architecture one of clk_1hz is
signal fout:std_logic;
begin
process(clk10k)
variable count:integer range 0 to 4999;
begin
if clk10k'event and clk10k='1' then
if count=4999 then
fout<=not fout;
count:=0;
else
count:=count+1;
end if;
end if;
end process;
clk1hz<=fout;
end one;
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