{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "global_clk " "Info: Assuming node \"global_clk\" is an undefined clock" {  } { { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "global_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "9 " "Warning: Found 9 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ad1674ctrl:143\|clkn " "Info: Detected gated clock \"ad1674ctrl:143\|clkn\" as buffer" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 10 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad1674ctrl:143\|clkn" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "ad1674ctrl:142\|clkn " "Info: Detected gated clock \"ad1674ctrl:142\|clkn\" as buffer" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 10 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad1674ctrl:142\|clkn" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ad1674ctrl:142\|current_state.st3 " "Info: Detected ripple clock \"ad1674ctrl:142\|current_state.st3\" as buffer" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad1674ctrl:142\|current_state.st3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ad1674ctrl:143\|current_state.st3 " "Info: Detected ripple clock \"ad1674ctrl:143\|current_state.st3\" as buffer" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad1674ctrl:143\|current_state.st3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ad1674ctrl:142\|current_state.st4 " "Info: Detected ripple clock \"ad1674ctrl:142\|current_state.st4\" as buffer" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad1674ctrl:142\|current_state.st4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ad1674ctrl:143\|current_state.st4 " "Info: Detected ripple clock \"ad1674ctrl:143\|current_state.st4\" as buffer" {  } { { "AD1674CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/AD1674CTRL.vhd" 16 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ad1674ctrl:143\|current_state.st4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "adc0809ctrl:117\|current_state.st6 " "Info: Detected ripple clock \"adc0809ctrl:117\|current_state.st6\" as buffer" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "adc0809ctrl:117\|current_state.st6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpinadc0809:130\|fout1 " "Info: Detected ripple clock \"fenpinadc0809:130\|fout1\" as buffer" {  } { { "FENPINADC0809.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINADC0809.vhd" 15 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpinadc0809:130\|fout1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fenpinpwm20M_10k:75\|fout1 " "Info: Detected ripple clock \"fenpinpwm20M_10k:75\|fout1\" as buffer" {  } { { "FENPINPWM20M_10K.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINPWM20M_10K.vhd" 16 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "fenpinpwm20M_10k:75\|fout1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "global_clk register adc0809ctrl:117\|regl\[3\] register bio_polor1:137\|pwm 28.57 MHz 35.0 ns Internal " "Info: Clock \"global_clk\" has Internal fmax of 28.57 MHz between source register \"adc0809ctrl:117\|regl\[3\]\" and destination register \"bio_polor1:137\|pwm\" (period= 35.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.500 ns + Longest register register " "Info: + Longest register to register delay is 26.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc0809ctrl:117\|regl\[3\] 1 REG LC1_A18 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A18; Fanout = 2; REG Node = 'adc0809ctrl:117\|regl\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns overcur_ctrl:139\|process0~183 2 COMB LC8_A18 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC8_A18; Fanout = 1; COMB Node = 'overcur_ctrl:139\|process0~183'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { adc0809ctrl:117|regl[3] overcur_ctrl:139|process0~183 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 6.900 ns overcur_ctrl:139\|process0~184 3 COMB LC5_A17 1 " "Info: 3: + IC(2.200 ns) + CELL(1.800 ns) = 6.900 ns; Loc. = LC5_A17; Fanout = 1; COMB Node = 'overcur_ctrl:139\|process0~184'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { overcur_ctrl:139|process0~183 overcur_ctrl:139|process0~184 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 9.800 ns overcur_ctrl:139\|process0~185 4 COMB LC8_A17 8 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC8_A17; Fanout = 8; COMB Node = 'overcur_ctrl:139\|process0~185'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { overcur_ctrl:139|process0~184 overcur_ctrl:139|process0~185 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 14.400 ns overcur_ctrl:139\|ctrl_out\[3\]~1326 5 COMB LC2_A13 2 " "Info: 5: + IC(2.300 ns) + CELL(2.300 ns) = 14.400 ns; Loc. = LC2_A13; Fanout = 2; COMB Node = 'overcur_ctrl:139\|ctrl_out\[3\]~1326'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { overcur_ctrl:139|process0~185 overcur_ctrl:139|ctrl_out[3]~1326 } "NODE_NAME" } } { "OVERCUR_CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/OVERCUR_CTRL.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 17.300 ns bio_polor1:137\|LessThan0~656 6 COMB LC5_A13 1 " "Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 17.300 ns; Loc. = LC5_A13; Fanout = 1; COMB Node = 'bio_polor1:137\|LessThan0~656'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { overcur_ctrl:139|ctrl_out[3]~1326 bio_polor1:137|LessThan0~656 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 19.700 ns bio_polor1:137\|LessThan0~659 7 COMB LC7_A13 1 " "Info: 7: + IC(0.600 ns) + CELL(1.800 ns) = 19.700 ns; Loc. = LC7_A13; Fanout = 1; COMB Node = 'bio_polor1:137\|LessThan0~659'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { bio_polor1:137|LessThan0~656 bio_polor1:137|LessThan0~659 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 22.600 ns bio_polor1:137\|LessThan0~661 8 COMB LC4_A13 1 " "Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 22.600 ns; Loc. = LC4_A13; Fanout = 1; COMB Node = 'bio_polor1:137\|LessThan0~661'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { bio_polor1:137|LessThan0~659 bio_polor1:137|LessThan0~661 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 26.500 ns bio_polor1:137\|pwm 9 REG LC1_A14 1 " "Info: 9: + IC(2.200 ns) + CELL(1.700 ns) = 26.500 ns; Loc. = LC1_A14; Fanout = 1; REG Node = 'bio_polor1:137\|pwm'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { bio_polor1:137|LessThan0~661 bio_polor1:137|pwm } "NODE_NAME" } } { "BIO_POLOR1.vhd" "" { Text "D:/my_eda4/fpga_program/BIO_POLOR1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.800 ns ( 63.40 % ) " "Info: Total cell delay = 16.800 ns ( 63.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.700 ns ( 36.60 % ) " "Info: Total interconnect delay = 9.700 ns ( 36.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "26.500 ns" { adc0809ctrl:117|regl[3] overcur_ctrl:139|process0~183 overcur_ctrl:139|process0~184 overcur_ctrl:139|process0~185 overcur_ctrl:139|ctrl_out[3]~1326 bio_polor1:137|LessThan0~656 bio_polor1:137|LessThan0~659 bio_polor1:137|LessThan0~661 bio_polor1:137|pwm } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "26.500 ns" { adc0809ctrl:117|regl[3] overcur_ctrl:139|process0~183 overcur_ctrl:139|process0~184 overcur_ctrl:139|process0~185 overcur_ctrl:139|ctrl_out[3]~1326 bio_polor1:137|LessThan0~656 bio_polor1:137|LessThan0~659 bio_polor1:137|LessThan0~661 bio_polor1:137|pwm } { 0.000ns 0.600ns 2.200ns 0.600ns 2.300ns 0.600ns 0.600ns 0.600ns 2.200ns } { 0.000ns 2.300ns 1.800ns 2.300ns 2.300ns 2.300ns 1.800ns 2.300ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.900 ns - Smallest " "Info: - Smallest clock skew is -4.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk destination 8.800 ns + Shortest register " "Info: + Shortest clock path from clock \"global_clk\" to destination register is 8.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns fenpinpwm20M_10k:75\|fout1 2 REG LC5_A24 10 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC5_A24; Fanout = 10; REG Node = 'fenpinpwm20M_10k:75\|fout1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { global_clk fenpinpwm20M_10k:75|fout1 } "NODE_NAME" } } { "FENPINPWM20M_10K.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINPWM20M_10K.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.000 ns) 8.800 ns bio_polor1:137\|pwm 3 REG LC1_A14 1 " "Info: 3: + IC(2.400 ns) + CELL(0.000 ns) = 8.800 ns; Loc. = LC1_A14; Fanout = 1; REG Node = 'bio_polor1:137\|pwm'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } "NODE_NAME" } } { "BIO_POLOR1.vhd" "" { Text "D:/my_eda4/fpga_program/BIO_POLOR1.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 44.32 % ) " "Info: Total cell delay = 3.900 ns ( 44.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 55.68 % ) " "Info: Total interconnect delay = 4.900 ns ( 55.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { global_clk fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.800 ns" { global_clk global_clk~out fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } { 0.000ns 0.000ns 2.500ns 2.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "global_clk source 13.700 ns - Longest register " "Info: - Longest clock path from clock \"global_clk\" to source register is 13.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns global_clk 1 CLK PIN_43 29 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 29; CLK Node = 'global_clk'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { global_clk } "NODE_NAME" } } { "yuanlitu.bdf" "" { Schematic "D:/my_eda4/fpga_program/yuanlitu.bdf" { { 624 184 352 640 "global_clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns fenpinadc0809:130\|fout1 2 REG LC2_C1 9 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_C1; Fanout = 9; REG Node = 'fenpinadc0809:130\|fout1'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { global_clk fenpinadc0809:130|fout1 } "NODE_NAME" } } { "FENPINADC0809.vhd" "" { Text "D:/my_eda4/fpga_program/FENPINADC0809.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(1.100 ns) 10.700 ns adc0809ctrl:117\|current_state.st6 3 REG LC8_A3 10 " "Info: 3: + IC(3.200 ns) + CELL(1.100 ns) = 10.700 ns; Loc. = LC8_A3; Fanout = 10; REG Node = 'adc0809ctrl:117\|current_state.st6'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(0.000 ns) 13.700 ns adc0809ctrl:117\|regl\[3\] 4 REG LC1_A18 2 " "Info: 4: + IC(3.000 ns) + CELL(0.000 ns) = 13.700 ns; Loc. = LC1_A18; Fanout = 2; REG Node = 'adc0809ctrl:117\|regl\[3\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 36.50 % ) " "Info: Total cell delay = 5.000 ns ( 36.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 63.50 % ) " "Info: Total interconnect delay = 8.700 ns ( 63.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.700 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.700 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 2.500ns 3.200ns 3.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { global_clk fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.800 ns" { global_clk global_clk~out fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } { 0.000ns 0.000ns 2.500ns 2.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.700 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.700 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 2.500ns 3.200ns 3.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ADC0809CTRL.vhd" "" { Text "D:/my_eda4/fpga_program/ADC0809CTRL.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "BIO_POLOR1.vhd" "" { Text "D:/my_eda4/fpga_program/BIO_POLOR1.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "26.500 ns" { adc0809ctrl:117|regl[3] overcur_ctrl:139|process0~183 overcur_ctrl:139|process0~184 overcur_ctrl:139|process0~185 overcur_ctrl:139|ctrl_out[3]~1326 bio_polor1:137|LessThan0~656 bio_polor1:137|LessThan0~659 bio_polor1:137|LessThan0~661 bio_polor1:137|pwm } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "26.500 ns" { adc0809ctrl:117|regl[3] overcur_ctrl:139|process0~183 overcur_ctrl:139|process0~184 overcur_ctrl:139|process0~185 overcur_ctrl:139|ctrl_out[3]~1326 bio_polor1:137|LessThan0~656 bio_polor1:137|LessThan0~659 bio_polor1:137|LessThan0~661 bio_polor1:137|pwm } { 0.000ns 0.600ns 2.200ns 0.600ns 2.300ns 0.600ns 0.600ns 0.600ns 2.200ns } { 0.000ns 2.300ns 1.800ns 2.300ns 2.300ns 2.300ns 1.800ns 2.300ns 1.700ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.800 ns" { global_clk fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.800 ns" { global_clk global_clk~out fenpinpwm20M_10k:75|fout1 bio_polor1:137|pwm } { 0.000ns 0.000ns 2.500ns 2.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.700 ns" { global_clk fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.700 ns" { global_clk global_clk~out fenpinadc0809:130|fout1 adc0809ctrl:117|current_state.st6 adc0809ctrl:117|regl[3] } { 0.000ns 0.000ns 2.500ns 3.200ns 3.000ns } { 0.000ns 2.800ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}