e:|altera|70|quartus|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]
}
# end
# entity
a_csnbuffer
# storage
db|FSK.(35).cnf
db|FSK.(35).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|a_csnbuffer.tdf
0a953daa377c9212d3c374d37725bd
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout6
-1
3
sout5
-1
3
sout4
-1
3
sout3
-1
3
sout2
-1
3
sout1
-1
3
sout0
-1
3
sin6
-1
3
sin5
-1
3
sin4
-1
3
sin3
-1
3
sin2
-1
3
sin1
-1
3
sin0
-1
3
ena
-1
3
cout6
-1
3
cout5
-1
3
cout4
-1
3
cout3
-1
3
cout2
-1
3
cout1
-1
3
cout0
-1
3
clrn
-1
3
clk
-1
3
cin6
-1
3
cin5
-1
3
cin4
-1
3
cin3
-1
3
cin2
-1
3
cin1
-1
3
cin0
-1
3
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node
}
# end
# entity
a_csnbuffer
# storage
db|FSK.(36).cnf
db|FSK.(36).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|a_csnbuffer.tdf
0a953daa377c9212d3c374d37725bd
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout0
-1
3
sin0
-1
3
ena
-1
3
clrn
-1
3
clk
-1
3
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:cout_node
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:cout_node
}
# end
# entity
addcore
# storage
db|FSK.(37).cnf
db|FSK.(37).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|addcore.tdf
a15afd3ef3a875c24a5fa0b7eda7718a
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
7
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
}
# used_port {
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
e:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|70|quartus|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
e:|altera|70|quartus|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]
}
# end
# entity
bypassff
# storage
db|FSK.(38).cnf
db|FSK.(38).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|bypassff.tdf
cc9f69a814877cd8d49717f2d06d44d9
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
}
# used_port {
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|bypassff:datab1_ff[1][1]
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|bypassff:datab1_ff[1][0]
}
# end
# entity
bypassff
# storage
db|FSK.(39).cnf
db|FSK.(39).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|bypassff.tdf
cc9f69a814877cd8d49717f2d06d44d9
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
}
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|bypassff:datab1_ff[0][1]
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|bypassff:datab1_ff[0][0]
}
# end
# entity
altshift
# storage
db|FSK.(40).cnf
db|FSK.(40).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|altshift.tdf
9741853922f7b354286beaabf56745
6
# user_parameter {
WIDTH
12
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
dds:ddsi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|altshift:result_ext_latency_ffs
}
# end
# entity
SRED
# storage
db|FSK.(41).cnf
db|FSK.(41).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|70|DSPBuilder|Altlib|DSPBUILDER.VHD
8db9848836c8bf84c562e781491b1a4a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
widthin
32
PARAMETER_SIGNED_DEC
USR
widthout
10
PARAMETER_SIGNED_DEC
USR
msb
31
PARAMETER_SIGNED_DEC
USR
lsb
22
PARAMETER_SIGNED_DEC
USR
round
0
PARAMETER_SIGNED_DEC
USR
satur
0
PARAMETER_SIGNED_DEC
USR
lpm_signed
BusIsSigned
PARAMETER_ENUM
USR
 constraint(xin)
31 downto 0
PARAMETER_STRING
USR
 constraint(yout)
9 downto 0
PARAMETER_STRING
USR
}
# include_file {
e:|altera|70|DSPBuilder|Altlib|DSPBUILDERPACK.VHD
d95346ffffa61212bd7a3a1d5243cd8
}
# hierarchies {
dds:ddsi|SRED:BusConversioni
}
# end
# entity
SRED
# storage
db|FSK.(42).cnf
db|FSK.(42).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|altera|70|DSPBuilder|Altlib|DSPBUILDER.VHD
8db9848836c8bf84c562e781491b1a4a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
widthin
20
PARAMETER_SIGNED_DEC
USR
widthout
10
PARAMETER_SIGNED_DEC
USR
msb
19
PARAMETER_SIGNED_DEC
USR
lsb
10
PARAMETER_SIGNED_DEC
USR
round
0
PARAMETER_SIGNED_DEC
USR
satur
0
PARAMETER_SIGNED_DEC
USR
lpm_signed
BusIsSigned
PARAMETER_ENUM
USR
 constraint(xin)
19 downto 0
PARAMETER_STRING
USR
 constraint(yout)
9 downto 0
PARAMETER_STRING
USR
}
# include_file {
e:|altera|70|DSPBuilder|Altlib|DSPBUILDERPACK.VHD
d95346ffffa61212bd7a3a1d5243cd8
}
# hierarchies {
dds:ddsi|SRED:BusConversion1i
}
# end
# entity
altsyncram
# storage
db|FSK.(43).cnf
db|FSK.(43).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|altsyncram.tdf
54ca23b6a4929c50f5115a9a53314c
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
10
PARAMETER_UNKNOWN
USR
WIDTHAD_A
10
PARAMETER_UNKNOWN
USR
NUMWORDS_A
1024
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
FSK0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_26u
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
e:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|70|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|altera|70|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
e:|altera|70|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|70|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
e:|altera|70|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
e:|altera|70|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
e:|altera|70|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
e:|altera|70|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_26u
# storage
db|FSK.(44).cnf
db|FSK.(44).cnf
# case_insensitive
# source_file
db|altsyncram_26u.tdf
dc28e5b8128487d8d654d371f4d6d891
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
FSK0.rtl.mif
cac7c60db7c4d40216bdbfcc378a6
}
# end
# entity
lpm_mult
# storage
db|FSK.(45).cnf
db|FSK.(45).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|lpm_mult.tdf
18aa2671c22d18e1c946169fa487586
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTHA
10
PARAMETER_UNKNOWN
USR
LPM_WIDTHB
10
PARAMETER_UNKNOWN
USR
LPM_WIDTHP
20
PARAMETER_UNKNOWN
USR
LPM_WIDTHR
20
PARAMETER_UNKNOWN
USR
LPM_WIDTHS
1
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
LATENCY
0
PARAMETER_UNKNOWN
DEF
INPUT_A_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
INPUT_B_IS_CONSTANT
NO
PARAMETER_UNKNOWN
USR
USE_EAB
OFF
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
6
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Stratix
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
APEX20K_TECHNOLOGY_MAPPER
LUT
TECH_MAPPER_APEX20K
USR
DEDICATED_MULTIPLIER_CIRCUITRY
AUTO
PARAMETER_UNKNOWN
USR
DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO
0
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
mult_2h01
PARAMETER_UNKNOWN
USR
INPUT_A_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
INPUT_B_FIXED_VALUE
Bx
PARAMETER_UNKNOWN
DEF
USE_AHDL_IMPLEMENTATION
OFF
PARAMETER_UNKNOWN
DEF
}
# used_port {
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# include_file {
e:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|70|quartus|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
e:|altera|70|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
e:|altera|70|quartus|libraries|megafunctions|multcore.inc
13b7e8bee916e23c5f79837e9c670
e:|altera|70|quartus|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
}
# end
# entity
mult_2h01
# storage
db|FSK.(46).cnf
db|FSK.(46).cnf
# case_insensitive
# source_file
db|mult_2h01.tdf
718b4ab241283983e3e336cd375c5
6
# user_parameter {
dataa_width
1
PARAMETER_UNKNOWN
DEF
datab_width
1
PARAMETER_UNKNOWN
DEF
datac_width
1
PARAMETER_UNKNOWN
DEF
datad_width
1
PARAMETER_UNKNOWN
DEF
dataout_width
72
PARAMETER_UNKNOWN
DEF
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# end
# entity
FSK
# storage
db|FSK.(0).cnf
db|FSK.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
FSK.vhd
1424d0c9f25e5ca1cd8f0e98dcef8c7
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# include_file {
e:|altera|70|DSPBuilder|Altlib|DSPBUILDERPACK.VHD
d95346ffffa61212bd7a3a1d5243cd8
}
# hierarchies {
|
}
# end
# entity
dds
# storage
db|FSK.(4).cnf
db|FSK.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
4b3f74b54af8f160973dd8acd9d48c6a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(aword)
9 downto 0
PARAMETER_STRING
USR
 constraint(fword)
31 downto 0
PARAMETER_STRING
USR
 constraint(pword)
7 downto 0
PARAMETER_STRING
USR
 constraint(sout)
9 downto 0
PARAMETER_STRING
USR
}
# include_file {
e:|altera|70|DSPBuilder|Altlib|DSPBUILDERPACK.VHD
d95346ffffa61212bd7a3a1d5243cd8
}
# hierarchies {
dds:ddsi
}
# end
# complete