?? ask.tan.qmsg
字號:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" { } { { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock memory dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9 register dds:ddsi\|AltiMult:Producti\|resdtb\[17\] 10.767 ns " "Info: Slack time is 10.767 ns for clock \"clock\" between source memory \"dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9\" and destination register \"dds:ddsi\|AltiMult:Producti\|resdtb\[17\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "108.31 MHz 9.233 ns " "Info: Fmax is 108.31 MHz (period= 9.233 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.718 ns + Largest memory register " "Info: + Largest memory to register requirement is 19.718 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.109 ns + Largest " "Info: + Largest clock skew is -0.109 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.332 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(0.537 ns) 2.332 ns dds:ddsi\|AltiMult:Producti\|resdtb\[17\] 3 REG LCFF_X15_Y7_N13 3 " "Info: 3: + IC(0.684 ns) + CELL(0.537 ns) = 2.332 ns; Loc. = LCFF_X15_Y7_N13; Fanout = 3; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[17\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.221 ns" { clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.44 % ) " "Info: Total cell delay = 1.526 ns ( 65.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.806 ns ( 34.56 % ) " "Info: Total interconnect delay = 0.806 ns ( 34.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.332 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } { 0.000ns 0.000ns 0.122ns 0.684ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.441 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.661 ns) 2.441 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9 3 MEM M4K_X23_Y12 4 " "Info: 3: + IC(0.669 ns) + CELL(0.661 ns) = 2.441 ns; Loc. = M4K_X23_Y12; Fanout = 4; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_icu.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_icu.tdf" 163 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 67.60 % ) " "Info: Total cell delay = 1.650 ns ( 67.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.791 ns ( 32.40 % ) " "Info: Total interconnect delay = 0.791 ns ( 32.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.441 ns" { clock clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.441 ns" { clock clock~combout clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } { 0.000ns 0.000ns 0.122ns 0.669ns } { 0.000ns 0.989ns 0.000ns 0.661ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.332 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } { 0.000ns 0.000ns 0.122ns 0.684ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.441 ns" { clock clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.441 ns" { clock clock~combout clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } { 0.000ns 0.000ns 0.122ns 0.669ns } { 0.000ns 0.989ns 0.000ns 0.661ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.209 ns - " "Info: - Micro clock to output delay of source is 0.209 ns" { } { { "db/altsyncram_icu.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_icu.tdf" 163 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.332 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } { 0.000ns 0.000ns 0.122ns 0.684ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.441 ns" { clock clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.441 ns" { clock clock~combout clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } { 0.000ns 0.000ns 0.122ns 0.669ns } { 0.000ns 0.989ns 0.000ns 0.661ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.951 ns - Longest memory register " "Info: - Longest memory to register delay is 8.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9 1 MEM M4K_X23_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X23_Y12; Fanout = 4; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|ram_block1a6~porta_address_reg9'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "db/altsyncram_icu.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_icu.tdf" 163 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.993 ns) 2.993 ns dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|q_a\[7\] 2 MEM M4K_X23_Y12 1 " "Info: 2: + IC(0.000 ns) + CELL(2.993 ns) = 2.993 ns; Loc. = M4K_X23_Y12; Fanout = 1; MEM Node = 'dds:ddsi\|altsyncram:Mux0_rtl_0\|altsyncram_icu:auto_generated\|q_a\[7\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.993 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[7] } "NODE_NAME" } } { "db/altsyncram_icu.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/altsyncram_icu.tdf" 40 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.203 ns) + CELL(0.150 ns) 4.346 ns dds:ddsi\|AltiMult:Producti\|dataaint~203 3 COMB LCCOMB_X15_Y8_N2 14 " "Info: 3: + IC(1.203 ns) + CELL(0.150 ns) = 4.346 ns; Loc. = LCCOMB_X15_Y8_N2; Fanout = 14; COMB Node = 'dds:ddsi\|AltiMult:Producti\|dataaint~203'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.353 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[7] dds:ddsi|AltiMult:Producti|dataaint~203 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1622 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(2.663 ns) 7.436 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|mac_mult1~DATAOUT17 4 COMB DSPMULT_X16_Y8_N0 1 " "Info: 4: + IC(0.427 ns) + CELL(2.663 ns) = 7.436 ns; Loc. = DSPMULT_X16_Y8_N0; Fanout = 1; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|mac_mult1~DATAOUT17'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { dds:ddsi|AltiMult:Producti|dataaint~203 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT17 } "NODE_NAME" } } { "db/mult_lm01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_lm01.tdf" 39 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.224 ns) 7.660 ns dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|result\[17\] 5 COMB DSPOUT_X16_Y8_N2 1 " "Info: 5: + IC(0.000 ns) + CELL(0.224 ns) = 7.660 ns; Loc. = DSPOUT_X16_Y8_N2; Fanout = 1; COMB Node = 'dds:ddsi\|AltiMult:Producti\|lpm_mult:Mult0\|mult_lm01:auto_generated\|result\[17\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.224 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT17 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[17] } "NODE_NAME" } } { "db/mult_lm01.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/mult_lm01.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.925 ns) + CELL(0.366 ns) 8.951 ns dds:ddsi\|AltiMult:Producti\|resdtb\[17\] 6 REG LCFF_X15_Y7_N13 3 " "Info: 6: + IC(0.925 ns) + CELL(0.366 ns) = 8.951 ns; Loc. = LCFF_X15_Y7_N13; Fanout = 3; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[17\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.291 ns" { dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[17] dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.396 ns ( 71.46 % ) " "Info: Total cell delay = 6.396 ns ( 71.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.555 ns ( 28.54 % ) " "Info: Total interconnect delay = 2.555 ns ( 28.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.951 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[7] dds:ddsi|AltiMult:Producti|dataaint~203 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT17 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[17] dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.951 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[7] dds:ddsi|AltiMult:Producti|dataaint~203 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT17 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[17] dds:ddsi|AltiMult:Producti|resdtb[17] } { 0.000ns 0.000ns 1.203ns 0.427ns 0.000ns 0.925ns } { 0.000ns 2.993ns 0.150ns 2.663ns 0.224ns 0.366ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.332 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[17] } { 0.000ns 0.000ns 0.122ns 0.684ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.441 ns" { clock clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.441 ns" { clock clock~combout clock~clkctrl dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 } { 0.000ns 0.000ns 0.122ns 0.669ns } { 0.000ns 0.989ns 0.000ns 0.661ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.951 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[7] dds:ddsi|AltiMult:Producti|dataaint~203 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT17 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[17] dds:ddsi|AltiMult:Producti|resdtb[17] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.951 ns" { dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|ram_block1a6~porta_address_reg9 dds:ddsi|altsyncram:Mux0_rtl_0|altsyncram_icu:auto_generated|q_a[7] dds:ddsi|AltiMult:Producti|dataaint~203 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|mac_mult1~DATAOUT17 dds:ddsi|AltiMult:Producti|lpm_mult:Mult0|mult_lm01:auto_generated|result[17] dds:ddsi|AltiMult:Producti|resdtb[17] } { 0.000ns 0.000ns 1.203ns 0.427ns 0.000ns 0.925ns } { 0.000ns 2.993ns 0.150ns 2.663ns 0.224ns 0.366ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\] register dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\] 531 ps " "Info: Minimum slack time is 531 ps for clock \"clock\" between source register \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]\" and destination register \"dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.547 ns + Shortest register register " "Info: + Shortest register to register delay is 0.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\] 1 REG LCFF_X18_Y7_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y7_N31; Fanout = 2; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.313 ns) + CELL(0.150 ns) 0.463 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]~138 2 COMB LCCOMB_X18_Y7_N30 1 " "Info: 2: + IC(0.313 ns) + CELL(0.150 ns) = 0.463 ns; Loc. = LCCOMB_X18_Y7_N30; Fanout = 1; COMB Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]~138'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.463 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]~138 } "NODE_NAME" } } { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.547 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\] 3 REG LCFF_X18_Y7_N31 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.547 ns; Loc. = LCFF_X18_Y7_N31; Fanout = 2; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]~138 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 42.78 % ) " "Info: Total cell delay = 0.234 ns ( 42.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.313 ns ( 57.22 % ) " "Info: Total interconnect delay = 0.313 ns ( 57.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.547 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]~138 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.547 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]~138 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.313ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.339 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.537 ns) 2.339 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\] 3 REG LCFF_X18_Y7_N31 2 " "Info: 3: + IC(0.691 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X18_Y7_N31; Fanout = 2; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.228 ns" { clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.24 % ) " "Info: Total cell delay = 1.526 ns ( 65.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.813 ns ( 34.76 % ) " "Info: Total interconnect delay = 0.813 ns ( 34.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.339 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 2.339 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.537 ns) 2.339 ns dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\] 3 REG LCFF_X18_Y7_N31 2 " "Info: 3: + IC(0.691 ns) + CELL(0.537 ns) = 2.339 ns; Loc. = LCFF_X18_Y7_N31; Fanout = 2; REG Node = 'dds:ddsi\|SAdderSub:ParallelAdderSubtractori\|lpm_add_sub:\\pip:genaa:U0\|add_sub_bph:auto_generated\|pipeline_dffe\[31\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.228 ns" { clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.24 % ) " "Info: Total cell delay = 1.526 ns ( 65.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.813 ns ( 34.76 % ) " "Info: Total interconnect delay = 0.813 ns ( 34.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "db/add_sub_bph.tdf" "" { Text "D:/my_eda3/ASK_FSK/db/add_sub_bph.tdf" 32 15 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.547 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]~138 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.547 ns" { dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31]~138 dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.313ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clock clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.339 ns" { clock clock~combout clock~clkctrl dds:ddsi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|add_sub_bph:auto_generated|pipeline_dffe[31] } { 0.000ns 0.000ns 0.122ns 0.691ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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