{ "Info" "ITDB_TSU_RESULT" "dds:ddsi\|AltiMult:Producti\|databint\[2\]~_Duplicate_2 data_in clock 5.919 ns register " "Info: tsu for register \"dds:ddsi\|AltiMult:Producti\|databint\[2\]~_Duplicate_2\" (data pin = \"data_in\", clock pin = \"clock\") is 5.919 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.273 ns + Longest pin register " "Info: + Longest pin to register delay is 8.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.840 ns) 0.840 ns data_in 1 PIN PIN_126 1 " "Info: 1: + IC(0.000 ns) + CELL(0.840 ns) = 0.840 ns; Loc. = PIN_126; Fanout = 1; PIN Node = 'data_in'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_in } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.145 ns) + CELL(0.438 ns) 6.423 ns dds:ddsi\|AltiMult:Producti\|databint~34 2 COMB LCCOMB_X15_Y7_N26 3 " "Info: 2: + IC(5.145 ns) + CELL(0.438 ns) = 6.423 ns; Loc. = LCCOMB_X15_Y7_N26; Fanout = 3; COMB Node = 'dds:ddsi\|AltiMult:Producti\|databint~34'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.583 ns" { data_in dds:ddsi|AltiMult:Producti|databint~34 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1623 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.977 ns) + CELL(0.873 ns) 8.273 ns dds:ddsi\|AltiMult:Producti\|databint\[2\]~_Duplicate_2 3 REG DSPMULT_X16_Y8_N0 12 " "Info: 3: + IC(0.977 ns) + CELL(0.873 ns) = 8.273 ns; Loc. = DSPMULT_X16_Y8_N0; Fanout = 12; REG Node = 'dds:ddsi\|AltiMult:Producti\|databint\[2\]~_Duplicate_2'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { dds:ddsi|AltiMult:Producti|databint~34 dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1665 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.151 ns ( 26.00 % ) " "Info: Total cell delay = 2.151 ns ( 26.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.122 ns ( 74.00 % ) " "Info: Total interconnect delay = 6.122 ns ( 74.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.273 ns" { data_in dds:ddsi|AltiMult:Producti|databint~34 dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.273 ns" { data_in data_in~combout dds:ddsi|AltiMult:Producti|databint~34 dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } { 0.000ns 0.000ns 5.145ns 0.977ns } { 0.000ns 0.840ns 0.438ns 0.873ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.047 ns + " "Info: + Micro setup delay of destination is 0.047 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1665 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.401 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.401 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.647 ns) + CELL(0.643 ns) 2.401 ns dds:ddsi\|AltiMult:Producti\|databint\[2\]~_Duplicate_2 3 REG DSPMULT_X16_Y8_N0 12 " "Info: 3: + IC(0.647 ns) + CELL(0.643 ns) = 2.401 ns; Loc. = DSPMULT_X16_Y8_N0; Fanout = 12; REG Node = 'dds:ddsi\|AltiMult:Producti\|databint\[2\]~_Duplicate_2'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.290 ns" { clock~clkctrl dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1665 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.632 ns ( 67.97 % ) " "Info: Total cell delay = 1.632 ns ( 67.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.769 ns ( 32.03 % ) " "Info: Total interconnect delay = 0.769 ns ( 32.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.401 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } { 0.000ns 0.000ns 0.122ns 0.647ns } { 0.000ns 0.989ns 0.000ns 0.643ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.273 ns" { data_in dds:ddsi|AltiMult:Producti|databint~34 dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.273 ns" { data_in data_in~combout dds:ddsi|AltiMult:Producti|databint~34 dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } { 0.000ns 0.000ns 5.145ns 0.977ns } { 0.000ns 0.840ns 0.438ns 0.873ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.401 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|databint[2]~_Duplicate_2 } { 0.000ns 0.000ns 0.122ns 0.647ns } { 0.000ns 0.989ns 0.000ns 0.643ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock data_out\[4\] dds:ddsi\|AltiMult:Producti\|resdtb\[14\] 7.135 ns register " "Info: tco from clock \"clock\" to destination pin \"data_out\[4\]\" through register \"dds:ddsi\|AltiMult:Producti\|resdtb\[14\]\" is 7.135 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.332 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.332 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.684 ns) + CELL(0.537 ns) 2.332 ns dds:ddsi\|AltiMult:Producti\|resdtb\[14\] 3 REG LCFF_X15_Y7_N15 1 " "Info: 3: + IC(0.684 ns) + CELL(0.537 ns) = 2.332 ns; Loc. = LCFF_X15_Y7_N15; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[14\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.221 ns" { clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.44 % ) " "Info: Total cell delay = 1.526 ns ( 65.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.806 ns ( 34.56 % ) " "Info: Total interconnect delay = 0.806 ns ( 34.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.332 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 0.122ns 0.684ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.553 ns + Longest register pin " "Info: + Longest register to pin delay is 4.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:ddsi\|AltiMult:Producti\|resdtb\[14\] 1 REG LCFF_X15_Y7_N15 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y7_N15; Fanout = 1; REG Node = 'dds:ddsi\|AltiMult:Producti\|resdtb\[14\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.755 ns) + CELL(2.798 ns) 4.553 ns data_out\[4\] 2 PIN PIN_136 0 " "Info: 2: + IC(1.755 ns) + CELL(2.798 ns) = 4.553 ns; Loc. = PIN_136; Fanout = 0; PIN Node = 'data_out\[4\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.553 ns" { dds:ddsi|AltiMult:Producti|resdtb[14] data_out[4] } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 61.45 % ) " "Info: Total cell delay = 2.798 ns ( 61.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.755 ns ( 38.55 % ) " "Info: Total interconnect delay = 1.755 ns ( 38.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.553 ns" { dds:ddsi|AltiMult:Producti|resdtb[14] data_out[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.553 ns" { dds:ddsi|AltiMult:Producti|resdtb[14] data_out[4] } { 0.000ns 1.755ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.332 ns" { clock clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[14] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.332 ns" { clock clock~combout clock~clkctrl dds:ddsi|AltiMult:Producti|resdtb[14] } { 0.000ns 0.000ns 0.122ns 0.684ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.553 ns" { dds:ddsi|AltiMult:Producti|resdtb[14] data_out[4] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.553 ns" { dds:ddsi|AltiMult:Producti|resdtb[14] data_out[4] } { 0.000ns 1.755ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dds:ddsi\|SDelay:Delayi\|result\[1\] Fword\[1\] clock 0.291 ns register " "Info: th for register \"dds:ddsi\|SDelay:Delayi\|result\[1\]\" (data pin = \"Fword\[1\]\", clock pin = \"clock\") is 0.291 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.355 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 116 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 116; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.537 ns) 2.355 ns dds:ddsi\|SDelay:Delayi\|result\[1\] 3 REG LCFF_X19_Y8_N27 2 " "Info: 3: + IC(0.707 ns) + CELL(0.537 ns) = 2.355 ns; Loc. = LCFF_X19_Y8_N27; Fanout = 2; REG Node = 'dds:ddsi\|SDelay:Delayi\|result\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { clock~clkctrl dds:ddsi|SDelay:Delayi|result[1] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.80 % ) " "Info: Total cell delay = 1.526 ns ( 64.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.829 ns ( 35.20 % ) " "Info: Total interconnect delay = 0.829 ns ( 35.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.355 ns" { clock clock~clkctrl dds:ddsi|SDelay:Delayi|result[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.355 ns" { clock clock~combout clock~clkctrl dds:ddsi|SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.122ns 0.707ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.330 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.330 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns Fword\[1\] 1 PIN PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'Fword\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Fword[1] } "NODE_NAME" } } { "ASK.vhd" "" { Text "D:/my_eda3/ASK_FSK/ASK.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.275 ns) 2.246 ns dds:ddsi\|SDelay:Delayi\|result~469 2 COMB LCCOMB_X19_Y8_N26 1 " "Info: 2: + IC(0.972 ns) + CELL(0.275 ns) = 2.246 ns; Loc. = LCCOMB_X19_Y8_N26; Fanout = 1; COMB Node = 'dds:ddsi\|SDelay:Delayi\|result~469'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { Fword[1] dds:ddsi|SDelay:Delayi|result~469 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1282 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.330 ns dds:ddsi\|SDelay:Delayi\|result\[1\] 3 REG LCFF_X19_Y8_N27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.330 ns; Loc. = LCFF_X19_Y8_N27; Fanout = 2; REG Node = 'dds:ddsi\|SDelay:Delayi\|result\[1\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dds:ddsi|SDelay:Delayi|result~469 dds:ddsi|SDelay:Delayi|result[1] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.358 ns ( 58.28 % ) " "Info: Total cell delay = 1.358 ns ( 58.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.972 ns ( 41.72 % ) " "Info: Total interconnect delay = 0.972 ns ( 41.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { Fword[1] dds:ddsi|SDelay:Delayi|result~469 dds:ddsi|SDelay:Delayi|result[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { Fword[1] Fword[1]~combout dds:ddsi|SDelay:Delayi|result~469 dds:ddsi|SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.972ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.355 ns" { clock clock~clkctrl dds:ddsi|SDelay:Delayi|result[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.355 ns" { clock clock~combout clock~clkctrl dds:ddsi|SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.122ns 0.707ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.330 ns" { Fword[1] dds:ddsi|SDelay:Delayi|result~469 dds:ddsi|SDelay:Delayi|result[1] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.330 ns" { Fword[1] Fword[1]~combout dds:ddsi|SDelay:Delayi|result~469 dds:ddsi|SDelay:Delayi|result[1] } { 0.000ns 0.000ns 0.972ns 0.000ns } { 0.000ns 0.999ns 0.275ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}