?? m.tan.rpt
字號:
Classic Timing Analyzer report for m
Wed May 09 15:50:14 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clock'
6. Clock Hold: 'clock'
7. tsu
8. tco
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------+--------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------+--------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.852 ns ; sclrp ; SDelay:Delayi|result[0] ; -- ; clock ; 0 ;
; Worst-case tco ; N/A ; None ; 5.785 ns ; SDelay:Delay2i|DelayLine[6][0] ; Output ; clock ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -3.519 ns ; sclrp ; SDelay:Delay1i|DelayLine[1][0] ; -- ; clock ; 0 ;
; Clock Setup: 'clock' ; 18.936 ns ; 50.00 MHz ( period = 20.000 ns ) ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; SDelay:Delay1i|DelayLine[1][0] ; SDelay:Delayi|result[0] ; clock ; clock ; 0 ;
; Clock Hold: 'clock' ; 0.517 ns ; 50.00 MHz ( period = 20.000 ns ) ; N/A ; SDelay:Delay1i|DelayLine[0][0] ; SDelay:Delay1i|DelayLine[1][0] ; clock ; clock ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+--------------------------------+--------------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5T144C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; fmax Requirement ; 20 ns ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock ; ; User Pin ; 50.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock' ;
+-----------+-----------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 18.936 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay1i|DelayLine[1][0] ; SDelay:Delayi|result[0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.850 ns ;
; 19.071 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delayi|result[0] ; SDelay:Delay1i|DelayLine[0][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.715 ns ;
; 19.239 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[6][0] ; SDelay:Delayi|result[0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.547 ns ;
; 19.240 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay1i|DelayLine[1][0] ; SDelay:Delay2i|DelayLine[0][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.546 ns ;
; 19.245 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[4][0] ; SDelay:Delay2i|DelayLine[5][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.541 ns ;
; 19.245 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[5][0] ; SDelay:Delay2i|DelayLine[6][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.541 ns ;
; 19.246 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[0][0] ; SDelay:Delay2i|DelayLine[1][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.540 ns ;
; 19.247 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[2][0] ; SDelay:Delay2i|DelayLine[3][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.539 ns ;
; 19.248 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[1][0] ; SDelay:Delay2i|DelayLine[2][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.538 ns ;
; 19.250 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay2i|DelayLine[3][0] ; SDelay:Delay2i|DelayLine[4][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.536 ns ;
; 19.253 ns ; Restricted to 420.17 MHz ( period = 2.38 ns ) ; SDelay:Delay1i|DelayLine[0][0] ; SDelay:Delay1i|DelayLine[1][0] ; clock ; clock ; 20.000 ns ; 19.786 ns ; 0.533 ns ;
+-----------+-----------------------------------------------+--------------------------------+--------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clock' ;
+---------------+--------------------------------+--------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+---------------+--------------------------------+--------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; 0.517 ns ; SDelay:Delay1i|DelayLine[0][0] ; SDelay:Delay1i|DelayLine[1][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.533 ns ;
; 0.520 ns ; SDelay:Delay2i|DelayLine[3][0] ; SDelay:Delay2i|DelayLine[4][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.536 ns ;
; 0.522 ns ; SDelay:Delay2i|DelayLine[1][0] ; SDelay:Delay2i|DelayLine[2][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.538 ns ;
; 0.523 ns ; SDelay:Delay2i|DelayLine[2][0] ; SDelay:Delay2i|DelayLine[3][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.539 ns ;
; 0.524 ns ; SDelay:Delay2i|DelayLine[0][0] ; SDelay:Delay2i|DelayLine[1][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.540 ns ;
; 0.525 ns ; SDelay:Delay2i|DelayLine[4][0] ; SDelay:Delay2i|DelayLine[5][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.541 ns ;
; 0.525 ns ; SDelay:Delay2i|DelayLine[5][0] ; SDelay:Delay2i|DelayLine[6][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.541 ns ;
; 0.530 ns ; SDelay:Delay1i|DelayLine[1][0] ; SDelay:Delay2i|DelayLine[0][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.546 ns ;
; 0.531 ns ; SDelay:Delay2i|DelayLine[6][0] ; SDelay:Delayi|result[0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.547 ns ;
; 0.699 ns ; SDelay:Delayi|result[0] ; SDelay:Delay1i|DelayLine[0][0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.715 ns ;
; 0.834 ns ; SDelay:Delay1i|DelayLine[1][0] ; SDelay:Delayi|result[0] ; clock ; clock ; 0.000 ns ; 0.016 ns ; 0.850 ns ;
+---------------+--------------------------------+--------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
+---------------------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+-------+--------------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-------+--------------------------------+----------+
; N/A ; None ; 3.852 ns ; sclrp ; SDelay:Delayi|result[0] ; clock ;
; N/A ; None ; 3.755 ns ; sclrp ; SDelay:Delay2i|DelayLine[4][0] ; clock ;
; N/A ; None ; 3.755 ns ; sclrp ; SDelay:Delay2i|DelayLine[3][0] ; clock ;
; N/A ; None ; 3.754 ns ; sclrp ; SDelay:Delay2i|DelayLine[6][0] ; clock ;
; N/A ; None ; 3.754 ns ; sclrp ; SDelay:Delay2i|DelayLine[2][0] ; clock ;
; N/A ; None ; 3.752 ns ; sclrp ; SDelay:Delay1i|DelayLine[0][0] ; clock ;
; N/A ; None ; 3.751 ns ; sclrp ; SDelay:Delay2i|DelayLine[1][0] ; clock ;
; N/A ; None ; 3.750 ns ; sclrp ; SDelay:Delay2i|DelayLine[5][0] ; clock ;
; N/A ; None ; 3.750 ns ; sclrp ; SDelay:Delay2i|DelayLine[0][0] ; clock ;
; N/A ; None ; 3.749 ns ; sclrp ; SDelay:Delay1i|DelayLine[1][0] ; clock ;
+-------+--------------+------------+-------+--------------------------------+----------+
+------------------------------------------------------------------------------------------+
; tco ;
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