?? m.tan.rpt
字號:
+-------+--------------+------------+--------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------------------------------+--------+------------+
; N/A ; None ; 5.785 ns ; SDelay:Delay2i|DelayLine[6][0] ; Output ; clock ;
+-------+--------------+------------+--------------------------------+--------+------------+
+---------------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-------+--------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-------+--------------------------------+----------+
; N/A ; None ; -3.519 ns ; sclrp ; SDelay:Delay1i|DelayLine[1][0] ; clock ;
; N/A ; None ; -3.520 ns ; sclrp ; SDelay:Delay2i|DelayLine[5][0] ; clock ;
; N/A ; None ; -3.520 ns ; sclrp ; SDelay:Delay2i|DelayLine[0][0] ; clock ;
; N/A ; None ; -3.521 ns ; sclrp ; SDelay:Delay2i|DelayLine[1][0] ; clock ;
; N/A ; None ; -3.522 ns ; sclrp ; SDelay:Delay1i|DelayLine[0][0] ; clock ;
; N/A ; None ; -3.524 ns ; sclrp ; SDelay:Delay2i|DelayLine[6][0] ; clock ;
; N/A ; None ; -3.524 ns ; sclrp ; SDelay:Delay2i|DelayLine[2][0] ; clock ;
; N/A ; None ; -3.525 ns ; sclrp ; SDelay:Delay2i|DelayLine[4][0] ; clock ;
; N/A ; None ; -3.525 ns ; sclrp ; SDelay:Delay2i|DelayLine[3][0] ; clock ;
; N/A ; None ; -3.622 ns ; sclrp ; SDelay:Delayi|result[0] ; clock ;
+---------------+-------------+-----------+-------+--------------------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Wed May 09 15:50:12 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off m -c m --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Slack time is 18.936 ns for clock "clock" between source register "SDelay:Delay1i|DelayLine[1][0]" and destination register "SDelay:Delayi|result[0]"
Info: Fmax is restricted to 420.17 MHz due to tcl and tch limits
Info: + Largest register to register requirement is 19.786 ns
Info: + Setup relationship between source and destination is 20.000 ns
Info: + Latch edge is 20.000 ns
Info: Clock period of Destination clock "clock" is 20.000 ns with offset of 0.000 ns and duty cycle of 50
Info: Multicycle Setup factor for Destination register is 1
Info: - Launch edge is 0.000 ns
Info: Clock period of Source clock "clock" is 20.000 ns with offset of 0.000 ns and duty cycle of 50
Info: Multicycle Setup factor for Source register is 1
Info: + Largest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi|result[0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: - Longest clock path from clock "clock" to source register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i|DelayLine[1][0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: - Micro clock to output delay of source is 0.250 ns
Info: - Micro setup delay of destination is -0.036 ns
Info: - Longest register to register delay is 0.850 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i|DelayLine[1][0]'
Info: 2: + IC(0.491 ns) + CELL(0.275 ns) = 0.766 ns; Loc. = LCCOMB_X1_Y4_N24; Fanout = 1; COMB Node = 'SDelay:Delayi|result~14'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.850 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi|result[0]'
Info: Total cell delay = 0.359 ns ( 42.24 % )
Info: Total interconnect delay = 0.491 ns ( 57.76 % )
Info: Minimum slack time is 517 ps for clock "clock" between source register "SDelay:Delay1i|DelayLine[0][0]" and destination register "SDelay:Delay1i|DelayLine[1][0]"
Info: + Shortest register to register delay is 0.533 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 1; REG Node = 'SDelay:Delay1i|DelayLine[0][0]'
Info: 2: + IC(0.299 ns) + CELL(0.150 ns) = 0.449 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'SDelay:Delay1i|DelayLine~21'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.533 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i|DelayLine[1][0]'
Info: Total cell delay = 0.234 ns ( 43.90 % )
Info: Total interconnect delay = 0.299 ns ( 56.10 % )
Info: - Smallest register to register requirement is 0.016 ns
Info: + Hold relationship between source and destination is 0.000 ns
Info: + Latch edge is 0.000 ns
Info: Clock period of Destination clock "clock" is 20.000 ns with offset of 0.000 ns and duty cycle of 50
Info: Multicycle Setup factor for Destination register is 1
Info: Multicycle Hold factor for Destination register is 1
Info: - Launch edge is 0.000 ns
Info: Clock period of Source clock "clock" is 20.000 ns with offset of 0.000 ns and duty cycle of 50
Info: Multicycle Setup factor for Source register is 1
Info: Multicycle Hold factor for Source register is 1
Info: + Smallest clock skew is 0.000 ns
Info: + Longest clock path from clock "clock" to destination register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i|DelayLine[1][0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: - Shortest clock path from clock "clock" to source register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N1; Fanout = 1; REG Node = 'SDelay:Delay1i|DelayLine[0][0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: - Micro clock to output delay of source is 0.250 ns
Info: + Micro hold delay of destination is 0.266 ns
Info: tsu for register "SDelay:Delayi|result[0]" (data pin = "sclrp", clock pin = "clock") is 3.852 ns
Info: + Longest pin to register delay is 6.237 ns
Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 10; PIN Node = 'sclrp'
Info: 2: + IC(4.917 ns) + CELL(0.376 ns) = 6.153 ns; Loc. = LCCOMB_X1_Y4_N24; Fanout = 1; COMB Node = 'SDelay:Delayi|result~14'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.237 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi|result[0]'
Info: Total cell delay = 1.320 ns ( 21.16 % )
Info: Total interconnect delay = 4.917 ns ( 78.84 % )
Info: + Micro setup delay of destination is -0.036 ns
Info: - Shortest clock path from clock "clock" to destination register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi|result[0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: tco from clock "clock" to destination pin "Output" through register "SDelay:Delay2i|DelayLine[6][0]" is 5.785 ns
Info: + Longest clock path from clock "clock" to source register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N31; Fanout = 2; REG Node = 'SDelay:Delay2i|DelayLine[6][0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: + Micro clock to output delay of source is 0.250 ns
Info: + Longest register to pin delay is 3.186 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N31; Fanout = 2; REG Node = 'SDelay:Delay2i|DelayLine[6][0]'
Info: 2: + IC(0.534 ns) + CELL(2.652 ns) = 3.186 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'Output'
Info: Total cell delay = 2.652 ns ( 83.24 % )
Info: Total interconnect delay = 0.534 ns ( 16.76 % )
Info: th for register "SDelay:Delay1i|DelayLine[1][0]" (data pin = "sclrp", clock pin = "clock") is -3.519 ns
Info: + Longest clock path from clock "clock" to destination register is 2.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'
Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'
Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i|DelayLine[1][0]'
Info: Total cell delay = 1.526 ns ( 64.96 % )
Info: Total interconnect delay = 0.823 ns ( 35.04 % )
Info: + Micro hold delay of destination is 0.266 ns
Info: - Shortest pin to register delay is 6.134 ns
Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 10; PIN Node = 'sclrp'
Info: 2: + IC(4.915 ns) + CELL(0.275 ns) = 6.050 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'SDelay:Delay1i|DelayLine~21'
Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.134 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i|DelayLine[1][0]'
Info: Total cell delay = 1.219 ns ( 19.87 % )
Info: Total interconnect delay = 4.915 ns ( 80.13 % )
Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 111 megabytes of memory during processing
Info: Processing ended: Wed May 09 15:50:14 2007
Info: Elapsed time: 00:00:02
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