{ "Info" "ITDB_TSU_RESULT" "SDelay:Delayi\|result\[0\] sclrp clock 3.852 ns register " "Info: tsu for register \"SDelay:Delayi\|result\[0\]\" (data pin = \"sclrp\", clock pin = \"clock\") is 3.852 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.237 ns + Longest pin register " "Info: + Longest pin to register delay is 6.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns sclrp 1 PIN PIN_42 10 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 10; PIN Node = 'sclrp'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.917 ns) + CELL(0.376 ns) 6.153 ns SDelay:Delayi\|result~14 2 COMB LCCOMB_X1_Y4_N24 1 " "Info: 2: + IC(4.917 ns) + CELL(0.376 ns) = 6.153 ns; Loc. = LCCOMB_X1_Y4_N24; Fanout = 1; COMB Node = 'SDelay:Delayi\|result~14'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.293 ns" { sclrp SDelay:Delayi|result~14 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1282 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.237 ns SDelay:Delayi\|result\[0\] 3 REG LCFF_X1_Y4_N25 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.237 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { SDelay:Delayi|result~14 SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 21.16 % ) " "Info: Total cell delay = 1.320 ns ( 21.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.917 ns ( 78.84 % ) " "Info: Total interconnect delay = 4.917 ns ( 78.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.237 ns" { sclrp SDelay:Delayi|result~14 SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.237 ns" { sclrp sclrp~combout SDelay:Delayi|result~14 SDelay:Delayi|result[0] } { 0.000ns 0.000ns 4.917ns 0.000ns } { 0.000ns 0.860ns 0.376ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.349 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delayi\|result\[0\] 3 REG LCFF_X1_Y4_N25 1 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N25; Fanout = 1; REG Node = 'SDelay:Delayi\|result\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.237 ns" { sclrp SDelay:Delayi|result~14 SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.237 ns" { sclrp sclrp~combout SDelay:Delayi|result~14 SDelay:Delayi|result[0] } { 0.000ns 0.000ns 4.917ns 0.000ns } { 0.000ns 0.860ns 0.376ns 0.084ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delayi|result[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delayi|result[0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock Output SDelay:Delay2i\|DelayLine\[6\]\[0\] 5.785 ns register " "Info: tco from clock \"clock\" to destination pin \"Output\" through register \"SDelay:Delay2i\|DelayLine\[6\]\[0\]\" is 5.785 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.349 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delay2i\|DelayLine\[6\]\[0\] 3 REG LCFF_X1_Y4_N31 2 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N31; Fanout = 2; REG Node = 'SDelay:Delay2i\|DelayLine\[6\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delay2i|DelayLine[6][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay2i|DelayLine[6][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay2i|DelayLine[6][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.186 ns + Longest register pin " "Info: + Longest register to pin delay is 3.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDelay:Delay2i\|DelayLine\[6\]\[0\] 1 REG LCFF_X1_Y4_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y4_N31; Fanout = 2; REG Node = 'SDelay:Delay2i\|DelayLine\[6\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SDelay:Delay2i|DelayLine[6][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(2.652 ns) 3.186 ns Output 2 PIN PIN_28 0 " "Info: 2: + IC(0.534 ns) + CELL(2.652 ns) = 3.186 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'Output'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.186 ns" { SDelay:Delay2i|DelayLine[6][0] Output } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.652 ns ( 83.24 % ) " "Info: Total cell delay = 2.652 ns ( 83.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.534 ns ( 16.76 % ) " "Info: Total interconnect delay = 0.534 ns ( 16.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.186 ns" { SDelay:Delay2i|DelayLine[6][0] Output } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.186 ns" { SDelay:Delay2i|DelayLine[6][0] Output } { 0.000ns 0.534ns } { 0.000ns 2.652ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay2i|DelayLine[6][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay2i|DelayLine[6][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.186 ns" { SDelay:Delay2i|DelayLine[6][0] Output } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.186 ns" { SDelay:Delay2i|DelayLine[6][0] Output } { 0.000ns 0.534ns } { 0.000ns 2.652ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "SDelay:Delay1i\|DelayLine\[1\]\[0\] sclrp clock -3.519 ns register " "Info: th for register \"SDelay:Delay1i\|DelayLine\[1\]\[0\]\" (data pin = \"sclrp\", clock pin = \"clock\") is -3.519 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.349 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.349 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clock 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clock'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clock~clkctrl 2 COMB CLKCTRL_G2 10 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 10; COMB Node = 'clock~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.537 ns) 2.349 ns SDelay:Delay1i\|DelayLine\[1\]\[0\] 3 REG LCFF_X1_Y4_N11 2 " "Info: 3: + IC(0.701 ns) + CELL(0.537 ns) = 2.349 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i\|DelayLine\[1\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.238 ns" { clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.96 % ) " "Info: Total cell delay = 1.526 ns ( 64.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 35.04 % ) " "Info: Total interconnect delay = 0.823 ns ( 35.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.134 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns sclrp 1 PIN PIN_42 10 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 10; PIN Node = 'sclrp'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclrp } "NODE_NAME" } } { "m.vhd" "" { Text "D:/my_eda3/m/m.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.915 ns) + CELL(0.275 ns) 6.050 ns SDelay:Delay1i\|DelayLine~21 2 COMB LCCOMB_X1_Y4_N10 1 " "Info: 2: + IC(4.915 ns) + CELL(0.275 ns) = 6.050 ns; Loc. = LCCOMB_X1_Y4_N10; Fanout = 1; COMB Node = 'SDelay:Delay1i\|DelayLine~21'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.190 ns" { sclrp SDelay:Delay1i|DelayLine~21 } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1289 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.134 ns SDelay:Delay1i\|DelayLine\[1\]\[0\] 3 REG LCFF_X1_Y4_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.134 ns; Loc. = LCFF_X1_Y4_N11; Fanout = 2; REG Node = 'SDelay:Delay1i\|DelayLine\[1\]\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1326 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns ( 19.87 % ) " "Info: Total cell delay = 1.219 ns ( 19.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.915 ns ( 80.13 % ) " "Info: Total interconnect delay = 4.915 ns ( 80.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.134 ns" { sclrp SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.134 ns" { sclrp sclrp~combout SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 4.915ns 0.000ns } { 0.000ns 0.860ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { clock clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.349 ns" { clock clock~combout clock~clkctrl SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 0.122ns 0.701ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.134 ns" { sclrp SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.134 ns" { sclrp sclrp~combout SDelay:Delay1i|DelayLine~21 SDelay:Delay1i|DelayLine[1][0] } { 0.000ns 0.000ns 4.915ns 0.000ns } { 0.000ns 0.860ns 0.275ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}