?? m1.mdl
字號:
Cell "CustomSymbolStrType"
Cell "CustomSymbolStrField"
Cell "CustomSymbolStrFcn"
Cell "CustomSymbolStrBlkIO"
Cell "CustomSymbolStrTmpVar"
Cell "CustomSymbolStrMacro"
PropName "DisabledProps"
}
Version "1.2.0"
ForceParamTrailComments off
GenerateComments on
IgnoreCustomStorageClasses on
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 13
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.2.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeERTFirstTime on
ERTFirstTimeCompliant off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "m1"
Location [2, 82, 1014, 721]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [295, 265, 325, 305]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "3"
clken off
MaskValue "1"
sclr on
SIGNALCOMPILER_PARAMS "depth;3;clken;off;MaskValue;1;sclr;on;"
}
Block {
BlockType Reference
Name "Delay1"
Ports [1, 1]
Position [445, 265, 475, 305]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "7"
clken off
MaskValue "1"
sclr on
}
Block {
BlockType Reference
Name "Output"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [535, 277, 600, 293]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Output Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
SIGNALCOMPILER_PARAMS "sgn;Single Bit;nodetype;Output Port;bwl;1;bwr;0"
";sat;off;rnd;off;cst;0;LocPin;any;"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [635, 269, 665, 301]
Floating off
Location [169, 429, 776, 669]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [554, 183, 623, 230]
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/SignalCompiler"
SourceType "SignalCompiler"
family "Cyclone II"
opt "Balanced"
synthtool "Others"
vstim on
SynthAct "None"
workdir "D:\\my_eda3\\m"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile off
SignalTapDepth "128"
VerilogSupport off
UniqueVHDLHierarchyName off
RegenerateIPFunctionalModel off
RunUpdatedSimulation off
JTAGCable "USB-Blaster [USB-0]"
dspb_ver "6.1"
}
Block {
BlockType Reference
Name "XOR"
Ports [2, 1]
Position [320, 179, 360, 206]
Orientation "left"
ForegroundColor "blue"
SourceBlock "allblocks_alteradspbuilder/Logical\nBit Operato"
"r"
SourceType "LogiBit AlteraBlockSet"
Operator "XOR"
Inputs "2"
SIGNALCOMPILER_PARAMS "Inputs;2;Operator;XOR;"
}
Line {
SrcBlock "XOR"
SrcPort 1
Points [-85, 0; 0, 90]
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "Delay1"
SrcPort 1
Points [0, 0; 20, 0]
Branch {
DstBlock "Output"
DstPort 1
}
Branch {
Points [0, -100]
DstBlock "XOR"
DstPort 1
}
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [85, 0]
Branch {
Points [0, -85]
DstBlock "XOR"
DstPort 2
}
Branch {
DstBlock "Delay1"
DstPort 1
}
}
Line {
SrcBlock "Output"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
}
}
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