Classic Timing Analyzer report for RS
Thu May 31 20:52:19 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.998 ns   ; r    ; qn ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 10.998 ns       ; r    ; qn ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu May 31 20:52:16 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off RS -c RS --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "q1~0" is a latch
Info: Longest tpd from source pin "r" to destination pin "qn" is 10.998 ns
    Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_24; Fanout = 2; PIN Node = 'r'
    Info: 2: + IC(5.293 ns) + CELL(0.651 ns) = 6.889 ns; Loc. = LCCOMB_X1_Y8_N28; Fanout = 1; COMB Node = 'qn1~0'
    Info: 3: + IC(1.053 ns) + CELL(3.056 ns) = 10.998 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'qn'
    Info: Total cell delay = 4.652 ns ( 42.30 % )
    Info: Total interconnect delay = 6.346 ns ( 57.70 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 103 megabytes of memory during processing
    Info: Processing ended: Thu May 31 20:52:19 2007
    Info: Elapsed time: 00:00:03