?? fifo_1.map.rpt
字號:
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------+
; FIFO_1.bdf ; yes ; User Block Diagram/Schematic File ; D:/my_eda/FIFO_1/FIFO_1.bdf ;
; lpm_fifo0.vhd ; yes ; Other ; D:/my_eda/FIFO_1/lpm_fifo0.vhd ;
; scfifo.tdf ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/scfifo.tdf ;
; a_regfifo.inc ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/a_regfifo.inc ;
; a_dpfifo.inc ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/a_dpfifo.inc ;
; a_i2fifo.inc ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/a_i2fifo.inc ;
; a_fffifo.inc ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/a_fffifo.inc ;
; a_f2fifo.inc ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/a_f2fifo.inc ;
; aglobal70.inc ; yes ; Megafunction ; e:/altera/quartus ii7.0/quartus/libraries/megafunctions/aglobal70.inc ;
; db/scfifo_4uv.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/scfifo_4uv.tdf ;
; db/a_dpfifo_b401.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/a_dpfifo_b401.tdf ;
; db/a_fefifo_m4f.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/a_fefifo_m4f.tdf ;
; db/cntr_oj7.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/cntr_oj7.tdf ;
; db/dpram_0it.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/dpram_0it.tdf ;
; db/altsyncram_urj1.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/altsyncram_urj1.tdf ;
; db/cntr_cjb.tdf ; yes ; Auto-Generated Megafunction ; D:/my_eda/FIFO_1/db/cntr_cjb.tdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 16 ;
; ; ;
; Total combinational functions ; 16 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 5 ;
; -- 3 input functions ; 2 ;
; -- <=2 input functions ; 9 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 10 ;
; -- arithmetic mode ; 6 ;
; ; ;
; Total registers ; 11 ;
; -- Dedicated logic registers ; 11 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 24 ;
; Total memory bits ; 64 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 19 ;
; Total fan-out ; 165 ;
; Average fan-out ; 2.80 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------+
; |FIFO_1 ; 16 (0) ; 11 (0) ; 64 ; 0 ; 0 ; 0 ; 24 ; 0 ; |FIFO_1 ;
; |lpm_fifo0:inst| ; 16 (0) ; 11 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst ;
; |scfifo:scfifo_component| ; 16 (0) ; 11 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component ;
; |scfifo_4uv:auto_generated| ; 16 (0) ; 11 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated ;
; |a_dpfifo_b401:dpfifo| ; 16 (2) ; 11 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo ;
; |a_fefifo_m4f:fifo_state| ; 8 (5) ; 5 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state ;
; |cntr_oj7:count_usedw| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw ;
; |cntr_cjb:rd_ptr_count| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count ;
; |cntr_cjb:wr_ptr| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr ;
; |dpram_0it:FIFOram| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram ;
; |altsyncram_urj1:altsyncram2| ; 0 (0) ; 0 (0) ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2 ;
+-------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8 ; 8 ; 8 ; 8 ; 64 ; None ;
+------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 11 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 9 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
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