JDF G
// Created by Project Navigator ver 1.0
PROJECT sdram_vhd_134
DESIGN sdram_vhd_134
DEVFAM virtex
DEVFAMTIME 0
DEVICE xcv300
DEVICETIME 1016218053
DEVPKG bg432
DEVPKGTIME 1016218053
DEVSPEED -6
DEVSPEEDTIME 1016218053
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
DOCUMENT functional_mti.do
DOCUMENT readme
DOCUMENT timing_mti.do
SOURCE brst_cntr.vhd
SOURCE rcd_cntr.vhd
SOURCE sys_int.vhd
SOURCE ref_cntr.vhd
SOURCE ki_cntr.vhd
SOURCE sdrmc_state.vhd
SOURCE sdrm.vhd
SOURCE sdrm_t.vhd
SOURCE cslt_cntr.vhd
SOURCE ihdlutil.vhd
SOURCE vrlgutil.vhd
STIMULUS sdrm_timing_tb.vhd
STIMULUS sdrm_functional_tb.vhd
DEPASSOC sdrm sdrm.ucf
[Normal]
p_CompxlibLang=xstvhd, virtex, Design.t_compLibraries, 1054756705, VHDL
p_CompxlibOutputDir=xstvhd, virtex, Design.t_compLibraries, 1054755730, C:\Modeltech_5.7c\xilinx_libs
p_CompxlibTargetSimulator=xstvhd, virtex, Design.t_compLibraries, 1054755730, ModelSim SE
p_ModelSimSimRunTime_tbw=xstvhd, virtex, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
p_ModelSimUutInstName_postMap=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostMapVhdlModel, 1054760703, sdrmc_INST
p_ModelSimUutInstName_postPar=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1054746748, sdrmc_INST
p_SimModelGenerateTestbenchFile=xstvhd, virtex, VHDL.t_postParSimModel, 1021322640, True
p_SimUseCustom_behav=xstvhd, virtex, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 1024088556, True
p_SimUseCustom_postMap=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostMapVhdlModel, 1024088598, True
p_SimUseCustom_postPar=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 991674470, True
p_SimUseCustom_postXlate=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1024088577, True
p_xstEquivRegRemoval=xstvhd, virtex, Schematic.t_synthesize, 1028847749, False
SynthOptEffort=leovhd, virtex, VHDL.t_synthesize, 1028851370, standard
SynthOptGoal=leovhd, virtex, VHDL.t_synthesize, 1028851370, delay
VirtexFamilyMapIOB=leovhd, virtex, VHDL.t_synthesize, 1028850801, True
xilxPAReffortLevel=xstvhd, virtex, Implementation.t_par, 991676686, High
xilxPARextraEffortLevel=xstvhd, virtex, Implementation.t_par, 991675250, Normal
xilxPostTrceSpeed=xstvhd, virtex, Implementation.t_postRouteTrce, 1021330912, -6
_VhdlSimCustom_behav=xstvhd, virtex, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 1024088556, functional_mti.do
_VhdlSimCustom_postMap=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostMapVhdlModel, 1024088598, func_map_mti.do
_VhdlSimCustom_postPar=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 991674470, timing_mti.do
_VhdlSimCustom_postXlate=xstvhd, virtex, VHDL Test Bench.t_MSimulatePostTranslateVhdlModel, 1024088577, func_translate_mti.do
_VhdlSimDo_behav=xstvhd, virtex, Bencher Waveform.t_MSimulateBehavioralVhdlModel, 1021330420, False
[STRATEGY-LIST]
Normal=True