`timescale 1ns / 1ps/*/////////////////////////////////////////////////////////////////////////////////// Company: 盛和科技// Engineer: 劉書超// // Create Date:    16:28:06 03/05/2008 // Design Name: // Module Name:    rece_7E // Project Name: // Target Devices: // Tool versions: // Description:    首先將輸入的并行8位數(shù)據(jù)通過移位寄存器轉(zhuǎn)變?yōu)?位串行數(shù)據(jù)，通過狀態(tài)機(jī)//                 檢測開始標(biāo)志7E，當(dāng)檢測到開始7E時，開始數(shù)據(jù)的去零和檢測結(jié)束標(biāo)志7E，//                 同時輸出8位數(shù)據(jù)。//// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ///////////////////////////////////////////////////////////////////////////////////*/module rece_7E(data,clk,rst,CHCLK,data_out,start_7E,z,error);     input          clk,                 rst,                 CHCLK;  input   [7:0]  data;                   output  [7:0]  data_out;  output         start_7E;        //start_7E為開始標(biāo)志7E的輸出  output         z;               //當(dāng)start_7E為7E時，Z為1    output         error;           //當(dāng)檢測到連續(xù)的7個1時，error置位，數(shù)據(jù)重發(fā)                   reg     [2:0]  state1;  reg     [3:0]  state2;  reg     [2:0]  count;  reg     [7:0]  _data_out,       //_data_out為數(shù)據(jù)輸出的中間寄存器，                 shift_out,       //shift_out為輸出數(shù)據(jù)移位寄存器                 _out,           //_out為檢測開始7E中間寄存器                 start_7E,                        shift_data;     //_data為輸入數(shù)據(jù)中間移位寄存器                                                               reg            out_data,        //out_data為檢測后數(shù)據(jù)輸出的中間寄存器,1位                 z,                 x;              //X為數(shù)據(jù)并串轉(zhuǎn)換后輸入檢測去零狀態(tài)機(jī)的中間寄存器					    parameter  IDLE=3'd0, A=3'd1,B=3'd2,C=3'd3,D=3'd4,E=3'd5,F=3'd6,G=3'd7;  parameter  DLE=4'd8,AB=4'd9,BC=4'd10,CD=4'd11,DE=4'd12,EF=4'd13,FG=4'd14;    always@(posedge clk)    begin      if(rst|shift_out=='h7E)          //shift_out為7E時，輸出數(shù)據(jù)信號Z置低        begin        z        <= 0;        start_7E <= 0;        end      else        if(state1=='d7&&x==0)          begin          start_7E <= 'h7E;          z        <= 1;          end    end    always@(posedge clk)               //檢測開始標(biāo)志字7E    begin      if(rst)        begin        state1 <= IDLE;                 //state1表示檢測開始標(biāo)志塊的狀態(tài)        state2 <= DLE;                  //state2表示檢測去0塊的狀態(tài)  	      end      else        if(z==0)          begin          casex(state1)            IDLE:  if(x==0)                     state1 <= A;                   else                     state1 <= IDLE;               A:  if(x==1)                     state1 <= B;                   else                     state1 <= IDLE;               B:  if(x==1)                     state1 <= C;                   else                     state1 <= IDLE;               C:  if(x==1)                     state1 <= D;                   else                     state1 <= IDLE;               D:  if(x==1)                     state1 <= E;                   else                     state1 <= IDLE;               E:  if(x==1)                     state1 <= F;                   else                     state1 <= IDLE;               F:  if(x==1)                     state1 <= G;                   else                     state1 <= IDLE;               G:  if(x==0)                     state1 <= IDLE;            default: state1 <= IDLE;          endcase          end    end    /*  輸入數(shù)據(jù)進(jìn)行移位轉(zhuǎn)換，data為輸入8位，x為輸入轉(zhuǎn)換后的一位串行數(shù)據(jù)  */  always@(posedge clk)     begin      if(rst)        shift_data <= 0;      else        if(CHCLK)          begin          shift_data <= data;          x          <= data[7];          end        else          begin          shift_data <= shift_data<<1;          x          <= shift_data[6];          end    end    always@(posedge clk)    begin      if(rst)        begin        count     <= 3'b110;        shift_out <= 0;        end      else        if(!(state2==EF&&x==0)&&z==1)                   //  傳送數(shù)據(jù)          begin          shift_out    <= shift_out<<1;                    //輸出數(shù)據(jù)移位寄存器          shift_out[0] <= out_data;          count        <= count+1;                 //通過count計數(shù)滿8位，使數(shù)據(jù)8位輸出          end    end    /*  /輸出中間移位寄存器來判斷是否輸出數(shù)據(jù)，當(dāng)不為7E時輸出8位數(shù)據(jù)  */  always@(posedge clk)    begin    if(rst)      _data_out <= 0;    else      if(!(shift_out==8'h7E) && z==1 && count==3'd7)        _data_out <= shift_out;                  //如果計算7E之間的數(shù)據(jù)，在此進(jìn)行計數(shù)    end    assign  data_out = _data_out;    always@(posedge clk)     //檢測數(shù)據(jù)去0和結(jié)束標(biāo)志7E    begin      if(rst)        out_data <= 0;      else        if(z==1)          casex(state2)            DLE: if(x==1)                   begin                   state2   <= AB;                   out_data <= x;                   end                 else                   begin                   state2   <= DLE;                   out_data <= x;                   end             AB: if(x==1)                   begin                   state2   <= BC;                   out_data <= x;                   end                 else                   begin                   state2   <= DLE;                   out_data <= x;                   end             BC: if(x==1)                   begin                   state2   <= CD;                   out_data <= x;                   end                 else                   begin                   state2   <= DLE;                   out_data <= x;                   end             CD: if(x==1)                   begin                   state2   <= DE;                   out_data <= x;                   end                 else                   begin                   state2   <= DLE;                   out_data <= x;                   end             DE: if(x==1)                   begin                   state2   <= EF;                   out_data <= x;                   end                 else                   begin                   state2   <= DLE;                   out_data <= x;                   end             EF: if(x==0)            //檢測到5個1，1個0，去0傳送數(shù)據(jù)                   state2   <= DLE;                 else                   begin                   state2   <= FG;                   out_data <= x;                   end             FG: if(x==0)                   begin                   state2   <= DLE;                   out_data <= x;                   end          default:state2<=DLE;        endcase    end  /*  當(dāng)檢測到7個連續(xù)的1，使error置位，數(shù)據(jù)重發(fā)  */  assign  error = (state2==FG&&x==1)?1:0;  endmodule