-------------------------------------------------------------------------------
--  File Name: ad7304.vhd
-------------------------------------------------------------------------------
--  Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |     author:    |   mod date:   | changes made:
--    V1.0    V.Ljubisavljevic    05 Mar 28     Initial release
--
-------------------------------------------------------------------------------
-- IMPORTANT
-- This model must be compiled without VITAL compliance checking
-------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:     CONVERTER_VHDL
--  Technology:  CMOS
--  Part:        AD7304
--  Description: 3V/5V, Rail to Rail, Quad, 8-Bit DAC
-------------------------------------------------------------------------------
-- NOTE
-- Hardware Shutdown SHDN mode is not implemented
-- because it is voltage dependent.
-- It is adopted for Output voltage in shutdown mode to be 0 V because it is
-- pooled down to ground through resistor of 120 ohms resistance.
-------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;

LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY ad7304 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CSNeg          :     VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK            :     VitalDelayType01 := VitalZeroDelay01;
        tipd_SDI            :     VitalDelayType01 := VitalZeroDelay01;
        tipd_LDACNeg        :     VitalDelayType01 := VitalZeroDelay01;
        tipd_CLRNeg         :     VitalDelayType01 := VitalZeroDelay01;
        -- tsetup values: setup times
        tsetup_CSNeg_CLK    :     VitalDelayType   := UnitDelay;
        tsetup_SDI_CLK      :     VitalDelayType   := UnitDelay;
        tsetup_LDACNeg_CLK  :     VitalDelayType   := UnitDelay;
        -- thold values: hold times
        thold_CSNeg_CLK     :     VitalDelayType   := UnitDelay;
        thold_SDI_CLK       :     VitalDelayType   := UnitDelay;
        thold_LDACNeg_CLK   :     VitalDelayType   := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge     :     VitalDelayType   := UnitDelay;
        tpw_CLK_negedge     :     VitalDelayType   := UnitDelay;
        tpw_CLRNeg_negedge  :     VitalDelayType   := UnitDelay;
        tpw_LDACNeg_negedge :     VitalDelayType   := UnitDelay;
        -- analog generics: values of Vref inputs In Volts
        Vdd                 :     real;
        Vss                 :     real;
        -- generic control parameters
        InstancePath        :     STRING           := DefaultInstancePath;
        TimingChecksOn      :     BOOLEAN          := DefaultTimingChecks;
        MsgOn               :     BOOLEAN          := DefaultMsgOn;
        XOn                 :     BOOLEAN          := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         :     STRING           := DefaultTimingModel
    );
    PORT (
        VrefA               : IN  real             := 0.0;
        VrefB               : IN  real             := 0.0;
        VrefC               : IN  real             := 0.0;
        VrefD               : IN  real             := 0.0;
        VOUTA               : OUT real             := 0.0;
        VOUTB               : OUT real             := 0.0;
        VOUTC               : OUT real             := 0.0;
        VOUTD               : OUT real             := 0.0;
        CLK                 : IN  std_ulogic       := 'U';
        CSNeg               : IN  std_ulogic       := 'U';
        SDI                 : IN  std_ulogic       := 'U';
        LDACNeg             : IN  std_ulogic       := 'U';
        CLRNeg              : IN  std_ulogic       := 'U'
    );

    ATTRIBUTE VITAL_LEVEL0 of ad7304 : ENTITY IS TRUE;
END ad7304;

-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ad7304 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID             : STRING  := "ad7304";
    CONSTANT resolution         : INTEGER := 8;

    SUBTYPE dacval_type IS NATURAL RANGE 0 TO (2**resolution-1);
    SUBTYPE stdl8 IS STD_LOGIC_VECTOR (resolution-1 DOWNTO 0);

    SIGNAL CLK_ipd     : std_ulogic := 'U';
    SIGNAL CSNeg_ipd   : std_ulogic := 'U';
    SIGNAL SDI_ipd     : std_ulogic := 'U';
    SIGNAL LDACNeg_ipd : std_ulogic := 'U';
    SIGNAL CLRNeg_ipd  : std_ulogic := 'U';

    SHARED VARIABLE PowerDown  : BOOLEAN := true;  -- True if power down is on
    SHARED VARIABLE PowerDownA : BOOLEAN := false;
    SHARED VARIABLE PowerDownB : BOOLEAN := false;
    SHARED VARIABLE PowerDownC : BOOLEAN := false;
    SHARED VARIABLE PowerDownD : BOOLEAN := false;

BEGIN

    ---------------------------------------------------------------------------
    -- Wire Delays
    ---------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN
        w_1 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_2 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
        w_3 : VitalWireDelay (SDI_ipd, SDI, tipd_SDI);
        w_4 : VitalWireDelay (LDACNeg_ipd, LDACNeg, tipd_LDACNeg);
        w_5 : VitalWireDelay (CLRNeg_ipd, CLRNeg, tipd_CLRNeg);
    END BLOCK;

    Behavior : BLOCK
        PORT (
            CLK     : IN  std_ulogic;
            CSNeg   : IN  std_ulogic;
            SDI     : IN  std_ulogic;
            LDACNeg : IN  std_ulogic;
            CLRNeg  : IN  std_ulogic);
        PORT MAP (
            CLK     => CLK_ipd,
            CSNeg   => CSNeg_ipd,
            SDI     => SDI_ipd,
            LDACNeg => LDACNeg_ipd,
            CLRNeg  => CLRNeg_ipd);

        CONSTANT tsettle : time := 2 us;
        CONSTANT tsdr : time := 2 us;   -- recovery from shutdown
        CONSTANT tsdn : time := 15 us;  -- time to shut down

        -- State machine state type
        TYPE state_type IS (DEFAULT, SERIAL);

        -- State machine current state
        SIGNAL current_state : state_type;
        -- Registers
        SIGNAL inregA        : stdl8     := (OTHERS => '0');
        SIGNAL inregB        : stdl8     := (OTHERS => '0');
        SIGNAL inregC        : stdl8     := (OTHERS => '0');
        SIGNAL inregD        : stdl8     := (OTHERS => '0');
        SIGNAL decregA       : stdl8     := (OTHERS => '0');
        SIGNAL decregB       : stdl8     := (OTHERS => '0');
        SIGNAL decregC       : stdl8     := (OTHERS => '0');
        SIGNAL decregD       : stdl8     := (OTHERS => '0');
        SIGNAL shift_reg     : STD_LOGIC_VECTOR(11 DOWNTO 0)
                                         := (OTHERS => '0');
        -- alias
        ALIAS SAC            : STD_LOGIC IS shift_reg(11);
        ALIAS SDC            : STD_LOGIC IS shift_reg(10);
        ALIAS Address        : STD_LOGIC_VECTOR(1 DOWNTO 0) IS
            shift_reg(9 DOWNTO 8);
        ALIAS Data           : stdl8 IS shift_reg(7 DOWNTO 0);
        -- Internal signals
        SIGNAL VOUTA_zd      : real      := 0.0;
        SIGNAL VOUTB_zd      : real      := 0.0;
        SIGNAL VOUTC_zd      : real      := 0.0;
        SIGNAL VOUTD_zd      : real      := 0.0;
        SIGNAL VrefA_int     : real;    -- Internal VrefA voltage
        SIGNAL VrefB_int     : real;
        SIGNAL VrefC_int     : real;
        SIGNAL VrefD_int     : real;
        -- model signals
        SIGNAL update        : BOOLEAN   := false;
        SIGNAL update_out    : BOOLEAN   := true;
        SIGNAL update_outA   : BOOLEAN   := false;
        SIGNAL update_outB   : BOOLEAN   := false;
        SIGNAL update_outC   : BOOLEAN   := false;
        SIGNAL update_outD   : BOOLEAN   := false;
        -- signals for upadating output
        SIGNAL settleA       : STD_LOGIC := '0';
        SIGNAL settleB       : STD_LOGIC := '0';
        SIGNAL settleC       : STD_LOGIC := '0';
        SIGNAL settleD       : STD_LOGIC := '0';

        -- Increment values for output
        SHARED VARIABLE StepA       : real := 0.0;
        SHARED VARIABLE StepB       : real := 0.0;
        SHARED VARIABLE StepC       : real := 0.0;
        SHARED VARIABLE StepD       : real := 0.0;
        --End values on outputs
        SHARED VARIABLE EndValA     : real := 0.0;
        SHARED VARIABLE EndValB     : real := 0.0;
        SHARED VARIABLE EndValC     : real := 0.0;
        SHARED VARIABLE EndValD     : real := 0.0;
        -- Pull up signals
        SIGNAL          CLK_nwv     : X01;
        SIGNAL          CSNeg_nwv   : X01;
        SIGNAL          SDI_nwv     : X01;
        SIGNAL          LDACNeg_nwv : X01;
        SIGNAL          CLRNeg_nwv  : X01;

        -- purpose: Calculate output voltage from 8 bit input
        PROCEDURE DAConvert (
            in_reg  : IN  stdl8;
            vref_in : IN  real;
            out_v   : OUT real) IS
        BEGIN  -- PROCEDURE DAConvert
            out_v := vref_in * (real(to_nat(in_reg)) / real(2**resolution));
        END PROCEDURE DAConvert;

    BEGIN
        CLK_nwv <=  to_X01(CLK);
        CSNeg_nwv <= to_X01(CSNeg);
        SDI_nwv <= to_X01(SDI);
        LDACNeg_nwv <= to_X01(LDACNeg);
        CLRNeg_nwv <= to_X01(CLRNeg);
        ----------------------------------------------------------------------
        -- Behavior Process
        ----------------------------------------------------------------------
        -- purpose: Determine current state
        -- type   : combinational
        -- inputs : CSNeg, CLRNeg
        state_decode: PROCESS (CSNeg_nwv, CLRNeg_nwv)
        BEGIN  -- PROCESS state_decode
            IF CLRNeg_nwv='1' THEN
                IF falling_edge(CSNeg_nwv) THEN
                    current_state <= SERIAL;
                ELSE
                    current_state <= DEFAULT;
                END IF;
            ELSE
                current_state <= DEFAULT;
            END IF;
        END PROCESS state_decode;

        -- purpose: Control of referent voltages
        -- type   : combinational
        -- inputs : VrefA, VrefB, VrefC, VrefD
        Vref_contorl: PROCESS (VrefA, VrefB, VrefC, VrefD)
            VARIABLE MaxV : real := Vdd;
            VARIABLE MinV : real := Vss;
        BEGIN  -- PROCESS Vref_contorl
            IF NOT (VrefA <= MaxV AND VrefA >= MinV) THEN
                ASSERT false
                    REPORT LF & InstancePath & partID & ": simulation may be"&