LF&"inaccurate due to VrefA range exceeding violations"
                    SEVERITY WARNING;
                -- If reference voltage is out of range
                -- set it to first closest valid value.
                IF VrefA > MaxV THEN
                    VrefA_int <= Vdd;
                ELSE
                    VrefA_int <= Vss;
                END IF;
            ELSE
                VrefA_int <= VrefA;
            END IF;
            IF NOT (VrefB <= MaxV AND VrefB >= MinV) THEN
                ASSERT false
                    REPORT LF & InstancePath & partID & ": simulation may be"&
                    LF&"inaccurate due to VrefB range exceeding violations"
                    SEVERITY WARNING;
                IF VrefB > MaxV THEN
                    VrefB_int <= Vdd;
                ELSE
                    VrefB_int <= Vss;
                END IF;
            ELSE
                VrefB_int <= VrefB;
            END IF;
            IF NOT (VrefC <= MaxV AND VrefC >= MinV) THEN
                ASSERT false
                    REPORT LF & InstancePath & partID & ": simulation may be"&
                    LF&"inaccurate due to VrefC range exceeding violations"
                    SEVERITY WARNING;
                -- If reference voltage is out of range
                -- set it to first closest valid value.
                IF VrefC > MaxV THEN
                    VrefC_int <= Vdd;
                ELSE
                    VrefC_int <= Vss;
                END IF;
            ELSE
                VrefC_int <= VrefC;
            END IF;
            IF NOT (VrefD <= MaxV AND VrefD >= MinV) THEN
                ASSERT false
                    REPORT LF & InstancePath & partID & ": simulation may be"&
                    LF&"inaccurate due to VrefD range exceeding violations"
                    SEVERITY WARNING;
                -- If reference voltage is out of range
                -- set it to first closest valid value.
                IF VrefD > MaxV THEN
                    VrefD_int <= Vdd;
                ELSE
                    VrefD_int <= Vss;
                END IF;
            ELSE
                VrefD_int <= VrefD;
            END IF;
        END PROCESS Vref_contorl;

        -- purpose: check for shut down mode
        -- type   : combinational
        -- inputs : update
        -- outputs:
        update_intreg: PROCESS (update) IS
        BEGIN  -- PROCESS update_intreg
            IF update THEN
                PowerDown := false;
                 IF SAC='0' THEN
                     PowerDown := true;
                 END IF;
                 IF SDC='0' THEN
                     CASE to_nat(Address) IS
                         WHEN 0 =>
                             PowerDownA := true;
                         WHEN 1 =>
                             PowerDownB := true;
                         WHEN 2 =>
                             PowerDownC := true;
                         WHEN 3 =>
                             PowerDownD := true;
                         WHEN OTHERS =>
                             NULL ;
                     END CASE;
                 ELSE
                     CASE to_nat(Address) IS
                         WHEN 0 =>
                             PowerDownA := false;
                         WHEN 1 =>
                             PowerDownB := false;
                         WHEN 2 =>
                             PowerDownC := false;
                         WHEN 3 =>
                             PowerDownD := false;
                         WHEN OTHERS =>
                             NULL ;
                     END CASE;
                 END IF;
            END IF;
            update_out <= NOT update_out;
        END PROCESS update_intreg;

        -- purpose: update DAC registers
        -- type   : combinational
        -- inputs : CLRNeg, LDACNeg, update, PowerDownD, PowerDownC,
        -- PowerDownB,  PowerDownA, PowerDown
        -- outputs: decregx
        hdw_cnt: PROCESS (CLRNeg_nwv, LDACNeg_nwv, update_out) IS
        BEGIN  -- PROCESS hdw_cnt
            IF (LDACNeg_nwv='0' AND CLRNeg_nwv='1') THEN
                IF NOT (PowerDown OR
                        (PowerDownA OR PowerDownB) OR
                        (PowerDownC OR PowerDownD))  THEN
                    decregA <= inregA;
                    decregB <= inregB;
                    decregC <= inregC;
                    decregD <= inregD;
                END IF;
            END IF;
            IF PowerDown THEN
                decregA <= (OTHERS => '0');
                decregB <= (OTHERS => '0');
                decregC <= (OTHERS => '0');
                decregD <= (OTHERS => '0');
            ELSE
                IF LDACNeg_nwv='0' THEN
                    decregA <= inregA;
                    decregB <= inregB;
                    decregC <= inregC;
                    decregD <= inregD;
                END IF;
                IF PowerDownA THEN
                    decregA <= (OTHERS => '0');
                END IF;
                IF PowerDownB THEN
                    decregB <= (OTHERS => '0');
                END IF;
                IF PowerDownC THEN
                    decregC <= (OTHERS => '0');
                END IF;
                IF PowerDownD THEN
                    decregD <= (OTHERS => '0');
                END IF;
            END if;
            IF CLRNeg_nwv='0' THEN
                decregA <= (OTHERS => '0');
                decregB <= (OTHERS => '0');
                decregC <= (OTHERS => '0');
                decregD <= (OTHERS => '0');
            END IF;
        END PROCESS hdw_cnt;

        digital : PROCESS (CLK_nwv, CSNeg_nwv, LDACNeg_nwv, CLRNeg_nwv)

            -- Timing Check Variables
            VARIABLE Tviol_CSNeg_CLK        : X01 := '0';
            VARIABLE TD_CSNeg_CLK           : VitalTimingDataType;

            VARIABLE Tviol_SDI_CLK          : X01 := '0';
            VARIABLE TD_SDI_CLK             : VitalTimingDataType;

            VARIABLE Tviol_LDACNeg_CLK      : X01 := '0';
            VARIABLE TD_LDACNeg_CLK         : VitalTimingDataType;

            VARIABLE PD_CLK                 : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_CLK              : X01 := '0';

            VARIABLE PD_CSNeg               : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_CSNeg            : X01 := '0';

            VARIABLE PD_LDACNeg             : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_LDACNeg          : X01 := '0';

            VARIABLE PD_CLRNeg              : VitalPeriodDataType :=
                VitalPeriodDataInit;
            VARIABLE Pviol_CLRNeg           : X01 := '0';

            VARIABLE Violation              : X01 := '0';

            -- purpose: Shift one data in shift reg in lsb position
            PROCEDURE shiftData (
                din : IN STD_LOGIC) IS
                VARIABLE tmp : STD_LOGIC_VECTOR(11 DOWNTO 0);
            BEGIN  -- PROCEDURE shiftData
                tmp := shift_reg;
                shift_reg(11 DOWNTO 1) <= tmp(10 DOWNTO 0);
                shift_reg(0) <= din;
            END PROCEDURE shiftData;

        BEGIN
            -------------------------------------------------------------------
            -- Timing Check Section
            -------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => CSNeg,
                    TestSignalName  => "CSNeg",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupLow        => tsetup_CSNeg_CLK,
                    HoldLow         => thold_CSNeg_CLK,
                    CheckEnabled    => true,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_CSNeg_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CSNeg_CLK
                    );

                VitalSetupHoldCheck (
                    TestSignal      => SDI,
                    TestSignalName  => "SDI",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_SDI_CLK,
                    SetupLow        => tsetup_SDI_CLK,
                    HoldHigh        => thold_SDI_CLK,
                    HoldLow         => thold_SDI_CLK,
                    CheckEnabled    => CSNeg = '0',
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_SDI_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_SDI_CLK
                    );

                VitalSetupHoldCheck (
                    TestSignal     => LDACNeg,
                    TestSignalName => "LDACNeg",
                    RefSignal      => CLK,
                    RefSignalName  => "CLK",
                    SetupHigh      => tsetup_LDACNeg_CLK,
                    HoldHigh       => thold_LDACNeg_CLK,
                    CheckEnabled   => true,
                    RefTransition  => '/',
                    HeaderMsg      => InstancePath & partID,
                    TimingData     => TD_LDACNeg_CLK,
                    XOn            => XOn,
                    MsgOn          => MsgOn,
                    Violation      => Tviol_LDACNeg_CLK
                    );

                VitalPeriodPulseCheck (
                    TestSignal     => CLK,
                    TestSignalName => "CLK",
                    PulseWidthHigh => tpw_CLK_posedge,
                    PulseWidthLow  => tpw_CLK_negedge,
                    HeaderMsg      => InstancePath & partID,
                    CheckEnabled   => current_state = SERIAL,
                    PeriodData     => PD_CLK,
                    XOn            => XOn,