VitalSetupHoldCheck (                TestSignal      => CDTI_ipd,                TestSignalName  => "CDTI",                RefSignal       => CCLK_ipd,                RefSignalName   => "CCLK",                SetupHigh       => tsetup_CDTI_CCLK,                SetupLow        => tsetup_CDTI_CCLK,                HoldHigh        => thold_CDTI_CCLK,                HoldLow         => thold_CDTI_CCLK,                CheckEnabled    => (SP_nwv = '0'),                RefTransition   => '/',                HeaderMsg       => InstancePath & partID,                TimingData      => TD_CDTI_CCLK,                XOn             => XOn,                MsgOn           => MsgOn,                Violation       => Tviol_CDTI_CCLK            );            VitalSetupHoldCheck (                TestSignal      => CSN_ipd,                TestSignalName  => "CSN",                RefSignal       => CCLK_ipd,                RefSignalName   => "CCLK",                SetupLow        => tsetup_CSN_CCLK,                HoldLow         => thold_CSN_CCLK,                CheckEnabled    => (SP_nwv = '0'),                RefTransition   => '/',                HeaderMsg       => InstancePath & partID,                TimingData      => TD_CSN_CCLK,                XOn             => XOn,                MsgOn           => MsgOn,                Violation       => Tviol_CSN_CCLK            );            VitalPeriodPulseCheck (                TestSignal      => CCLK_ipd,                TestSignalName  => "CCLK",                Period          => tperiod_CCLK,                PulseWidthLow   => tpw_CCLK_negedge,                PulseWidthHigh  => tpw_CCLK_posedge,                PeriodData      => TD_CCLK,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => TRUE,                Violation       => Pviol_CCLK );            VitalPeriodPulseCheck (                TestSignal      => BICK_ipd,                TestSignalName  => "BICK",                Period          => tperiod_BICKN,                PulseWidthLow   => tpw_BICK_negedge,                PulseWidthHigh  => tpw_BICK_posedge,                PeriodData      => TD_BICKN,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => (DFS = '0'),                Violation       => Pviol_BICKN );            VitalPeriodPulseCheck (                TestSignal      => BICK_ipd,                TestSignalName  => "BICK",                Period          => tperiod_BICKD,                PulseWidthLow   => tpw_BICK_negedge,                PulseWidthHigh  => tpw_BICK_posedge,                PeriodData      => TD_BICKD,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => (DFS = '1'),                Violation       => Pviol_BICKD );            VitalPeriodPulseCheck (                TestSignal      => CSN_ipd,                TestSignalName  => "CSN",                PulseWidthHigh  => tpw_CSN_posedge,                PeriodData      => TD_CSN,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => (SP_nwv = '0'),                Violation       => Pviol_CSN );            VitalPeriodPulseCheck (                TestSignal      => PDNNeg,                TestSignalName  => "PDNNeg",                PulseWidthLow   => tpw_PDNNeg_negedge,                PeriodData      => TD_PDNNeg,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => TRUE,                Violation       => Pviol_PDNNeg );            VitalPeriodPulseCheck (                TestSignal      => LRCK,                TestSignalName  => "LRCK",                Period          => tperiod_LRCK,                PeriodData      => TD_LRCK,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => TRUE,                Violation       => Pviol_LRCK );            VitalPeriodPulseCheck (                TestSignal      => MCLK,                TestSignalName  => "MCLK",                Period          => tperiod_MCLK,                PeriodData      => TD_MCLK,                XOn             => XOn,                MsgOn           => MsgOn,                HeaderMsg       => InstancePath & PartID,                CheckEnabled    => TRUE,                Violation       => Pviol_MCLK );            Violation := Tviol_SDTI_BICK OR Tviol_LRCK_BICK OR                         Tviol_CDTI_CCLK OR Tviol_CSN_CCLK OR Pviol_CCLK OR                         Pviol_BICKN OR Pviol_BICKD OR Pviol_CSN OR                         Pviol_PDNNeg OR Pviol_LRCK OR Pviol_MCLK;            ASSERT Violation = '0'                REPORT InstancePath & partID & ": simulation may be" &                       " inaccurate due to timing violations"                SEVERITY Warning;        END IF;    ----------------------------------------------------------------------------    -- Functionality Section    ----------------------------------------------------------------------------    --Mode control Interface    IF PDNNeg_nwv = '0' THEN        control1 := "00001111";        control2 := "00000010";        Mode := 3;        Pwdn <= '1';        Reset <= '1';        SMUTE <= '0';        DFS <= '0';    ELSIF SP_nwv = '0' AND not(MOff) THEN   --serial control mode        IF CSN_nwv = '0' AND rising_edge(CCLK_ipd) THEN --clock in            FOR I IN 15 DOWNTO 1 LOOP                inreg(i) := inreg(i-1);            END LOOP;            inreg(0) := CDTI_nwv;        ELSIF rising_edge(CSN_ipd) AND CCLK_nwv = '1' THEN            IF inreg(15 downto 13) = "011" THEN                IF inreg(12 downto 8) = "00000" THEN                    control1 := inreg(7 downto 0);                    Mode := to_nat(control1(4 downto 2));                    Pwdn <= control1(1);                    Reset <= control1(0);                ELSIF inreg(12 downto 8) = "00001" THEN                    control2 := inreg(7 downto 0);                    SMUTE <= control2(0);                    DFS <= control2(3);                ELSE                    ASSERT false                        REPORT InstancePath & partID & ": For addresses" &                        " from 02H to 1FH, data must not be written"                        SEVERITY Warning;                END IF;            ELSE                ASSERT false                    REPORT InstancePath & partID & ": Does not support " &                    " the read command and chip address"                    SEVERITY Warning;            END IF;        END IF;    END IF;    IF SP_nwv = '1' THEN     -- parallel control mode        IF CSN_nwv = '1' THEN            SMUTE <= '1';-- outputs soft-muted        ELSE            SMUTE <= '0';        END IF;        IF CCLK_nwv = '1' THEN            DFS <= '1'; --double speed        ELSE            DFS <= '0'; --normal speed        END IF;        IF CDTI_nwv = '1' THEN            Mode := 3;        ELSE            Mode := 2;        END IF;    END IF;    IF falling_edge(Reset) AND SP_nwv = '0' THEN        DZF <= '1';        ResetOn := true;        ResetOff := false;    END IF;    IF falling_edge(Smute) THEN        SmuteOff := true;    END IF;    --Audio Data Interface    IF PDNNeg_nwv = '0' OR Pwdn = '0' OR not(Powerup) THEN        --power-down        DZF <= '0';        delaycnt := 0;        delaycnt1 := 0;        dzfcnt := 0;        ResetOn := false;    ELSIF RSTN = '0' THEN   --reset        DZF <= '1';        IF rising_edge(Reset) THEN            ResetOff := true;        END IF;        IF ResetOff = true THEN            IF rising_edge(LRCK_ipd) THEN                delaycnt1 := delaycnt1 + 1;                IF delaycnt1 = 3 THEN                    delaycnt1 := 0;                    RSTN <= '1';                END IF;            END IF;        END IF;    ELSIF rising_edge(LRCK_ipd) THEN        CASE Mode IS            WHEN 0 => Rchreg0 := RchData(15 downto 0);                      TmpR := REAL(to_int(Rchreg0(15 downto 0)));                      Lchreg0 := LchData(15 downto 0);                      TmpL := REAL(to_int(Lchreg0(15 downto 0)));                      size := 15;            WHEN 1 => Rchreg1 := RchData(19 downto 0);                      TmpR := REAL(to_int(Rchreg1(19 downto 0)));                      Lchreg1 := LchData(19 downto 0);                      TmpL := REAL(to_int(Lchreg1(19 downto 0)));                      size := 19;            WHEN 2 => Rchreg := RchData(31 downto 8);                      TmpR := REAL(to_int(Rchreg(23 downto 0)));                      Lchreg := LchData(31 downto 8);                      TmpL := REAL(to_int(Lchreg(23 downto 0)));                      size := 23;            WHEN 3 => Rchreg := LchData(30 downto 7);                      TmpR := REAL(to_int(Rchreg(23 downto 0)));                      Lchreg := RchData(30 downto 7);                      TmpL := REAL(to_int(Lchreg(23 downto 0)));                      size := 23;            WHEN 4 => Rchreg := RchData(23 downto 0);                      TmpR := REAL(to_int(Rchreg(23 downto 0)));                      Lchreg := LchData(23 downto 0);                      TmpL := REAL(to_int(Lchreg(23 downto 0)));                      size := 23;        END CASE;        TmpR := TmpR * 1.7 * Vref / (5.0 * REAL(2**(size) - 1));        TmpL := TmpL * 1.7 * Vref / (5.0 * REAL(2**(size) - 1));        IF Smute = '1' OR rising_edge(Smute) THEN -- Soft mute            IF smutecnt = 1024 THEN                TmpR := 0.0;                TmpL := 0.0;            ELSE    --step -0.125dB                smutecnt := smutecnt + 1;                TmpR := TmpR * (0.9857119 ** smutecnt);                TmpL := TmpL * (0.9857119 ** smutecnt);            END IF;        ELSIF Smute = '0' AND SmuteOff THEN            smutecnt := smutecnt - 1;            TmpR := TmpR * (0.9857119 ** smutecnt);            TmpL := TmpL * (0.9857119 ** smutecnt);            IF smutecnt = 0 THEN                SmuteOff := false;            END IF;        END IF;        IF ResetOn THEN    -- Internal reset            delaycnt := delaycnt + 1;            IF delaycnt = 4 THEN                delaycnt := 0;                RSTN <= '0';                ResetOn := false;            END IF;        END IF;        IF TmpR = 0.0 AND TmpL = 0.0 THEN   --zero detection            IF dzfcnt = 8192 THEN                DZF <= '1';            ELSE                dzfcnt := dzfcnt + 1;            END IF;        ELSIF Reset = '1' AND not(ResetOff) THEN            dzfcnt := 0;            DZF <= '0';        END IF;        IF ResetOff THEN            delaycnt2 := delaycnt2 + 1;            IF delaycnt2 = 2 THEN                delaycnt2 := 0;                DZF <=  '0';                ResetOff := false;                dzfcnt := 0;            END IF;        END IF;        AOUTR_zd := VCOM +TmpR;        AOUTL_zd := VCOM +TmpL;        AOUTR_zd19 <= AOUTR_zd18;        AOUTR_zd18 := AOUTR_zd17;        AOUTR_zd17 := AOUTR_zd16;        AOUTR_zd16 := AOUTR_zd15;        AOUTR_zd15 := AOUTR_zd14;        AOUTR_zd14 := AOUTR_zd13;        AOUTR_zd13 := AOUTR_zd12;        AOUTR_zd12 := AOUTR_zd11;        AOUTR_zd11 := AOUTR_zd10;        AOUTR_zd10 := AOUTR_zd9;        AOUTR_zd9 := AOUTR_zd8;        AOUTR_zd8 := AOUTR_zd7;        AOUTR_zd7 := AOUTR_zd6;        AOUTR_zd6 := AOUTR_zd5;        AOUTR_zd5 := AOUTR_zd4;        AOUTR_zd4 := AOUTR_zd3;        AOUTR_zd3 := AOUTR_zd2;        AOUTR_zd2 := AOUTR_zd1;        AOUTR_zd1 := AOUTR_zd;        AOUTL_zd19 <= AOUTL_zd18;        AOUTL_zd18 := AOUTL_zd17;        AOUTL_zd17 := AOUTL_zd16;        AOUTL_zd16 := AOUTL_zd15;        AOUTL_zd15 := AOUTL_zd14;        AOUTL_zd14 := AOUTL_zd13;        AOUTL_zd13 := AOUTL_zd12;        AOUTL_zd12 := AOUTL_zd11;        AOUTL_zd11 := AOUTL_zd10;        AOUTL_zd10 := AOUTL_zd9;        AOUTL_zd9 := AOUTL_zd8;        AOUTL_zd8 := AOUTL_zd7;        AOUTL_zd7 := AOUTL_zd6;        AOUTL_zd6 := AOUTL_zd5;        AOUTL_zd5 := AOUTL_zd4;        AOUTL_zd4 := AOUTL_zd3;        AOUTL_zd3 := AOUTL_zd2;        AOUTL_zd2 := AOUTL_zd1;        AOUTL_zd1 := AOUTL_zd;    ELSIF LRCK_nwv = '1' THEN        IF rising_edge(BICK_ipd) THEN            FOR I IN 31 DOWNTO 1 LOOP   -- LRCK=fs, BICK=64fs                LchData(i) := LchData(i-1);            END LOOP;            LchData(0) := SDTI_nwv;        END IF;    ELSIF LRCK_nwv = '0' THEN        IF rising_edge(BICK_ipd) THEN            FOR I IN 31 DOWNTO 1 LOOP   -- LRCK=fs, BICK=64fs                RchData(i) := RchData(i-1);            END LOOP;            RchData(0) := SDTI_nwv;        END IF;    END IF;    END PROCESS Behavior;    AnalogOut : PROCESS(PDNNeg_ipd, Pwdn, Powerup, RSTN, LRCK_ipd)    BEGIN        IF to_X01(PDNNeg_ipd) = '0' OR Pwdn = '0' OR not(Powerup) THEN            AOUTR <= 0.0;        ELSIF RSTN = '0' THEN            AOUTR <= VCOM;        ELSIF rising_edge(LRCK_ipd) THEN            AOUTR <= AOUTR_zd19 AFTER 0.1 * Period;        END IF;        IF to_X01(PDNNeg_ipd) = '0' OR Pwdn = '0' OR not(Powerup) THEN            AOUTL <= 0.0;        ELSIF RSTN = '0' THEN            AOUTL <= VCOM;        ELSIF rising_edge(LRCK_ipd) THEN            AOUTL <= AOUTL_zd19 AFTER 0.1 * Period;        END IF;   END PROCESS AnalogOut;    END BLOCK;END vhdl_behavioral;