?? top_vhd.sdo
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// Copyright (C) 1991-2003 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only
// to program PLD devices (but not masked PLD devices) from Altera. Any
// other use of such megafunction design, netlist, support information,
// device programming or simulation file, or any other related documentation
// or information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to the
// intellectual property, including patents, copyrights, trademarks, trade
// secrets, or maskworks, embodied in any such megafunction design, netlist,
// support information, device programming or simulation file, or any other
// related documentation or information provided by Altera or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.
//
// Device: Altera EP1S25F780C5 Package FBGA780
//
//
// This SDF file should be used for ModelSim-Altera (VHDL output from Quartus II) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "top")
(DATE "09/23/2003 14:35:41")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 3.0 Build 220 07/30/2003 Service Pack 1 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a34_a_aI.in_reg )
(DELAY
(ABSOLUTE
(PORT datain (1100:1100:1100) (1100:1100:1100) )
(PORT clk (1623:1623:1623) (1623:1623:1623) )
(PORT ena (2393:2393:2393) (2393:2393:2393) )
(PORT areset (2906:2906:2906) (2906:2906:2906) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
(SETUP ena (posedge clk) (276:276:276) )
(HOLD ena (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a34_a_aI.out_reg )
(DELAY
(ABSOLUTE
(PORT datain (1257:1257:1257) (1257:1257:1257) )
(PORT clk (1573:1573:1573) (1573:1573:1573) )
(PORT areset (2876:2876:2876) (2876:2876:2876) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a34_a_aI.oe_reg )
(DELAY
(ABSOLUTE
(PORT datain (2458:2458:2458) (2458:2458:2458) )
(PORT clk (1638:1638:1638) (1638:1638:1638) )
(PORT areset (2892:2892:2892) (2892:2892:2892) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_asynch_io" )
(INSTANCE DQ_a34_a_aI.inst1 )
(DELAY
(ABSOLUTE
(PORT oe (1678:1678:1678) (1678:1678:1678) )
(IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
(IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
(IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
(IOPATH regin regout (0:0:0) (0:0:0) )
)
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a28_a_aI.in_reg )
(DELAY
(ABSOLUTE
(PORT datain (1100:1100:1100) (1100:1100:1100) )
(PORT clk (1623:1623:1623) (1623:1623:1623) )
(PORT ena (2393:2393:2393) (2393:2393:2393) )
(PORT areset (2906:2906:2906) (2906:2906:2906) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
(SETUP ena (posedge clk) (276:276:276) )
(HOLD ena (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a28_a_aI.out_reg )
(DELAY
(ABSOLUTE
(PORT datain (1079:1079:1079) (1079:1079:1079) )
(PORT clk (1573:1573:1573) (1573:1573:1573) )
(PORT areset (2876:2876:2876) (2876:2876:2876) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a28_a_aI.oe_reg )
(DELAY
(ABSOLUTE
(PORT datain (2458:2458:2458) (2458:2458:2458) )
(PORT clk (1638:1638:1638) (1638:1638:1638) )
(PORT areset (2892:2892:2892) (2892:2892:2892) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_asynch_io" )
(INSTANCE DQ_a28_a_aI.inst1 )
(DELAY
(ABSOLUTE
(PORT oe (1678:1678:1678) (1678:1678:1678) )
(IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
(IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
(IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
(IOPATH regin regout (0:0:0) (0:0:0) )
)
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a23_a_aI.in_reg )
(DELAY
(ABSOLUTE
(PORT datain (1100:1100:1100) (1100:1100:1100) )
(PORT clk (1623:1623:1623) (1623:1623:1623) )
(PORT ena (2393:2393:2393) (2393:2393:2393) )
(PORT areset (2906:2906:2906) (2906:2906:2906) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
(SETUP ena (posedge clk) (276:276:276) )
(HOLD ena (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a23_a_aI.out_reg )
(DELAY
(ABSOLUTE
(PORT datain (1072:1072:1072) (1072:1072:1072) )
(PORT clk (1573:1573:1573) (1573:1573:1573) )
(PORT areset (2876:2876:2876) (2876:2876:2876) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a23_a_aI.oe_reg )
(DELAY
(ABSOLUTE
(PORT datain (2458:2458:2458) (2458:2458:2458) )
(PORT clk (1638:1638:1638) (1638:1638:1638) )
(PORT areset (2892:2892:2892) (2892:2892:2892) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_asynch_io" )
(INSTANCE DQ_a23_a_aI.inst1 )
(DELAY
(ABSOLUTE
(PORT oe (1678:1678:1678) (1678:1678:1678) )
(IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
(IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
(IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
(IOPATH regin regout (0:0:0) (0:0:0) )
)
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a22_a_aI.in_reg )
(DELAY
(ABSOLUTE
(PORT datain (1100:1100:1100) (1100:1100:1100) )
(PORT clk (1623:1623:1623) (1623:1623:1623) )
(PORT ena (2393:2393:2393) (2393:2393:2393) )
(PORT areset (2906:2906:2906) (2906:2906:2906) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
(SETUP ena (posedge clk) (276:276:276) )
(HOLD ena (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a22_a_aI.out_reg )
(DELAY
(ABSOLUTE
(PORT datain (1071:1071:1071) (1071:1071:1071) )
(PORT clk (1573:1573:1573) (1573:1573:1573) )
(PORT areset (2876:2876:2876) (2876:2876:2876) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a22_a_aI.oe_reg )
(DELAY
(ABSOLUTE
(PORT datain (2458:2458:2458) (2458:2458:2458) )
(PORT clk (1638:1638:1638) (1638:1638:1638) )
(PORT areset (2892:2892:2892) (2892:2892:2892) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_asynch_io" )
(INSTANCE DQ_a22_a_aI.inst1 )
(DELAY
(ABSOLUTE
(PORT oe (1678:1678:1678) (1678:1678:1678) )
(IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
(IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
(IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
(IOPATH regin regout (0:0:0) (0:0:0) )
)
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a0_a_aI.in_reg )
(DELAY
(ABSOLUTE
(PORT datain (978:978:978) (978:978:978) )
(PORT clk (1695:1695:1695) (1695:1695:1695) )
(PORT ena (2462:2462:2462) (2462:2462:2462) )
(PORT areset (2958:2958:2958) (2958:2958:2958) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
(SETUP ena (posedge clk) (276:276:276) )
(HOLD ena (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a0_a_aI.out_reg )
(DELAY
(ABSOLUTE
(PORT datain (1393:1393:1393) (1393:1393:1393) )
(PORT clk (1598:1598:1598) (1598:1598:1598) )
(PORT areset (2973:2973:2973) (2973:2973:2973) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a0_a_aI.oe_reg )
(DELAY
(ABSOLUTE
(PORT datain (2506:2506:2506) (2506:2506:2506) )
(PORT clk (1641:1641:1641) (1641:1641:1641) )
(PORT areset (2954:2954:2954) (2954:2954:2954) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (276:276:276) )
(HOLD datain (posedge clk) (64:64:64) )
)
)
(CELL
(CELLTYPE "stratix_asynch_io" )
(INSTANCE DQ_a0_a_aI.inst1 )
(DELAY
(ABSOLUTE
(PORT oe (1990:1990:1990) (1990:1990:1990) )
(IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
(IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
(IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
(IOPATH regin regout (0:0:0) (0:0:0) )
)
)
)
(CELL
(CELLTYPE "stratix_io_register" )
(INSTANCE DQ_a26_a_aI.in_reg )
(DELAY
(ABSOLUTE
(PORT datain (978:978:978) (978:978:978) )
(PORT clk (1695:1695:1695) (1695:1695:1695) )
(PORT ena (2357:2357:2357) (2357:2357:2357) )
(PORT areset (3022:3022:3022) (3022:3022:3022) )
(IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
(IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
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