?? frequency_divider.fit.rpt
字號:
; Fin ; PIN_10 ; 9 ; Global clock ; GCLK2 ;
+------+----------+---------+----------------------+------------------+
+---------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------------+-------------+
; Name ; Fan-Out ;
+-------------------+-------------+
; j[6]~213 ; 8 ;
; j[4]~198 ; 3 ;
; Reset_N ; 2 ;
; reduce_nor~41 ; 2 ;
; j[7] ; 2 ;
; j[6] ; 2 ;
; j[5] ; 2 ;
; j[4] ; 2 ;
; reduce_nor~40 ; 2 ;
; j[3] ; 2 ;
; j[0] ; 2 ;
; j[2] ; 2 ;
; j[1] ; 2 ;
; Fout~reg0 ; 2 ;
; j[6]~206COUT1_219 ; 1 ;
; j[6]~206 ; 1 ;
; j[5]~202COUT1_218 ; 1 ;
; j[5]~202 ; 1 ;
; j[3]~194COUT1 ; 1 ;
; j[3]~194 ; 1 ;
; j[0]~190COUT1_215 ; 1 ;
; j[0]~190 ; 1 ;
; j[2]~186COUT1_217 ; 1 ;
; j[2]~186 ; 1 ;
; j[1]~182COUT1_216 ; 1 ;
; j[1]~182 ; 1 ;
+-------------------+-------------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 0 / 8,840 ( 0 % ) ;
; Direct links ; 7 / 11,506 ( < 1 % ) ;
; Global clocks ; 1 / 8 ( 12 % ) ;
; LAB clocks ; 1 / 156 ( < 1 % ) ;
; LUT chains ; 0 / 2,619 ( 0 % ) ;
; Local interconnects ; 9 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 1 / 7,520 ( < 1 % ) ;
+----------------------------+----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 6.00) ; Number of LABs (Total = 2) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 2) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 2 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 6.00) ; Number of LABs (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 3.50) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 5.00) ; Number of LABs (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sun Aug 17 15:20:53 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Frequency_divider -c Frequency_divider
Info: Selected device EP1C3T100C6 for design "Frequency_divider"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: No exact pin location assignment(s) for 3 pins of 3 total pins
Info: Pin Fout not assigned to an exact location on the device
Info: Pin Reset_N not assigned to an exact location on the device
Info: Pin Fin not assigned to an exact location on the device
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted signal "Fin" to use Global clock in PIN 10
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 11 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 2.620 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y2; Fanout = 3; REG Node = 'j[4]'
Info: 2: + IC(0.288 ns) + CELL(0.454 ns) = 0.742 ns; Loc. = LAB_X1_Y2; Fanout = 2; COMB Node = 'reduce_nor~41'
Info: 3: + IC(0.462 ns) + CELL(0.225 ns) = 1.429 ns; Loc. = LAB_X2_Y2; Fanout = 8; COMB Node = 'j[6]~213'
Info: 4: + IC(0.335 ns) + CELL(0.856 ns) = 2.620 ns; Loc. = LAB_X2_Y2; Fanout = 4; REG Node = 'j[1]'
Info: Total cell delay = 1.535 ns ( 58.59 % )
Info: Total interconnect delay = 1.085 ns ( 41.41 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Aug 17 15:20:55 2008
Info: Elapsed time: 00:00:02
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