Constraints file: fifo2.pcfLoading device database for application Par from file "fifo2_map.ncd".   "fifo2" is an NCD, version 2.38, device xc3s200, package pq208, speed -4Loading device for application Par from file '3s200.nph' in environment
C:/Xilinx.Device speed data version:  PREVIEW 1.26 2003-06-19.Device utilization summary:   Number of External IOBs            24 out of 141    17%      Number of LOCed External IOBs    0 out of 24      0%   Number of SLICELs                  14 out of 1920    1%   Number of SLICEMs                   8 out of 960     1%   Number of BUFGMUXs                  2 out of 8      25%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98973f) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8..Phase 5.8 (Checksum:98ef8f) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file fifo2.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 218 unrouted;       REAL time: 0 secs Phase 2: 196 unrouted;       REAL time: 0 secs Phase 3: 55 unrouted;       REAL time: 0 secs Phase 4: 0 unrouted;       REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+|        rclk_BUFGP       |  BUFGMUX0| No   |    5 |  0.007     |  0.366      |+-------------------------+----------+------+------+------------+-------------+|        wclk_BUFGP       |  BUFGMUX1| No   |   15 |  0.039     |  0.386      |+-------------------------+----------+------+------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 98The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.692   The MAXIMUM PIN DELAY IS:                               2.373   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.437   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------         169          44           5           0           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  58 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file fifo2.ncd.PAR done.