Project Navigator Auto-Make Log File-------------------------------------



Started process "Check Syntax".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "async_cmp.v"Module <async_cmp> compiledCompiling source file "fifomem2.v"Compiling source file "rptr_empty2.v"Module <fifomem2> compiledModule <rptr_empty2> compiledCompiling source file "wptr_full2.v"Module <wptr_full2> compiledCompiling source file "fifo2.v"Module <fifo2> compiledNo errors in compilationAnalysis of file <fifo2.prj> succeeded. Completed process "Check Syntax".

Project Navigator Auto-Make Log File-------------------------------------

Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "async_cmp.v"Module <async_cmp> compiledCompiling source file "fifomem2.v"Compiling source file "rptr_empty2.v"Module <fifomem2> compiledModule <rptr_empty2> compiledCompiling source file "wptr_full2.v"Module <wptr_full2> compiledCompiling source file "fifo2.v"Module <fifo2> compiledNo errors in compilationAnalysis of file <fifo2.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <fifo2>.Module <fifo2> is correct for synthesis. Analyzing module <async_cmp>.Module <async_cmp> is correct for synthesis. Analyzing module <fifomem2>.Module <fifomem2> is correct for synthesis. Analyzing module <rptr_empty2>.Module <rptr_empty2> is correct for synthesis. Analyzing module <wptr_full2>.Module <wptr_full2> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <wptr_full2>.    Related source file is wptr_full2.v.    Found 4-bit register for signal <wptr>.    Found 1-bit register for signal <wfull>.    Found 4-bit adder for signal <$n0002> created at line 25.    Found 1-bit xor2 for signal <$n0003> created at line 26.    Found 1-bit xor2 for signal <$n0004> created at line 26.    Found 1-bit xor2 for signal <$n0005> created at line 26.    Found 4-bit register for signal <wbin>.    Found 1-bit register for signal <wfull2>.    Found 4 1-bit 2-to-1 multiplexers.    Summary:	inferred  10 D-type flip-flop(s).	inferred   1 Adder/Subtracter(s).	inferred   4 Multiplexer(s).Unit <wptr_full2> synthesized.Synthesizing Unit <rptr_empty2>.    Related source file is rptr_empty2.v.    Found 1-bit register for signal <rempty>.    Found 4-bit register for signal <rptr>.    Found 4-bit adder for signal <$n0002> created at line 25.    Found 1-bit xor2 for signal <$n0003> created at line 26.    Found 1-bit xor2 for signal <$n0004> created at line 26.    Found 1-bit xor2 for signal <$n0005> created at line 26.    Found 4-bit register for signal <rbin>.    Found 1-bit register for signal <rempty2>.    Found 4 1-bit 2-to-1 multiplexers.    Summary:	inferred  10 D-type flip-flop(s).	inferred   1 Adder/Subtracter(s).	inferred   4 Multiplexer(s).Unit <rptr_empty2> synthesized.Synthesizing Unit <fifomem2>.    Related source file is fifomem2.v.    Found 16x8-bit dual-port distributed RAM for signal <MEM>.    -----------------------------------------------------------------------    | aspect ratio       | 16-word x 8-bit                     |          |    | clock              | connected to signal <wclk>          | rise     |    | write enable       | connected to signal <wclken>        | high     |    | address            | connected to signal <waddr>         |          |    | dual address       | connected to signal <raddr>         |          |    | data in            | connected to signal <wdata>         |          |    | data out           | not connected                       |          |    | dual data out      | connected to signal <rdata>         |          |    | ram_style          | Auto                                |          |    -----------------------------------------------------------------------INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.    Summary:	inferred   1 RAM(s).Unit <fifomem2> synthesized.Synthesizing Unit <async_cmp>.    Related source file is async_cmp.v.    Found 4-bit comparator equal for signal <$n0003> created at line 20.    Found 1-bit xor2 for signal <$n0011> created at line 10.    Found 1-bit xor2 for signal <$n0012> created at line 10.    Summary:	inferred   1 Comparator(s).Unit <async_cmp> synthesized.Synthesizing Unit <fifo2>.    Related source file is fifo2.v.WARNING:Xst:1780 - Signal <raddr> is never used or assigned.WARNING:Xst:1780 - Signal <waddr> is never used or assigned.Unit <fifo2> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# RAMs                             : 1  16x8-bit dual-port distributed RAM: 1# Registers                        : 8  4-bit register                   : 4  1-bit register                   : 4# Multiplexers                     : 2  2-to-1 multiplexer               : 2# Adders/Subtractors               : 2  4-bit adder                      : 2# Comparators                      : 1  4-bit comparator equal           : 1# Xors                             : 8  1-bit xor2                       : 8==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <fifo2> ...Optimizing unit <async_cmp> ...Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Register rptr_empty2_rbin_3 equivalent to rptr_empty2_rptr_3 has been removedRegister wptr_full2_wbin_3 equivalent to wptr_full2_wptr_3 has been removedFound area constraint ratio of 100 (+ 5) on block fifo2, actual ratio is 1.FlipFlop wptr_full2_wptr_1 has been replicated 1 time(s)FlipFlop wptr_full2_wptr_3 has been replicated 1 time(s)FlipFlop wptr_full2_wptr_2 has been replicated 1 time(s)=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 3s200pq208-4  Number of Slices:                      28  out of   1920     1%   Number of Slice Flip Flops:            21  out of   3840     0%   Number of 4 input LUTs:                37  out of   3840     0%   Number of bonded IOBs:                 22  out of    141    15%   Number of GCLKs:                        2  out of      8    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+wclk                               | BUFGP                  | 20    |rclk                               | BUFGP                  | 9     |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 4.516ns (Maximum Frequency: 221.435MHz)   Minimum input arrival time before clock: 4.987ns   Maximum output required time after clock: 7.886ns   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd c:\xilinx\bin\fifo/_ngo -i -pxc3s200-pq208-4 fifo2.ngc fifo2.ngd Reading NGO file "C:/Xilinx/bin/fifo/fifo2.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Total memory usage is 40076 kilobytesWriting NGD file "fifo2.ngd" ...Writing NGDBUILD log file "fifo2.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "3s200pq208-4".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors:      0Number of warnings:    8Logic Utilization:  Number of Slice Flip Flops:          21 out of   3,840    1%  Number of 4 input LUTs:              27 out of   3,840    1%Logic Distribution:  Number of occupied Slices:                           22 out of   1,920    1%    Number of Slices containing only related logic:      22 out of      22  100%    Number of Slices containing unrelated logic:          0 out of      22    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:             43 out of   3,840    1%  Number used as logic:                 27  Number used for Dual Port RAMs:       16    (Two LUTs used per Dual Port RAM)  Number of bonded IOBs:               24 out of     141   17%  Number of GCLKs:                     2 out of       8   25%Total equivalent gate count for design:  1,360Additional JTAG gate count for IOBs:  1,152Peak Memory Usage:  69 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Mapping completed.See MAP report file "fifo2_map.mrp" for details.Completed process "Map".Mapping Module fifo2 . . .
MAP command line:
map -intstyle ise -p xc3s200-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o fifo2_map.ncd fifo2.ngd fifo2.pcf
Mapping Module fifo2: DONE


Started process "Place & Route".Constraints file: fifo2.pcfLoading device database for application Par from file "fifo2_map.ncd".   "fifo2" is an NCD, version 2.38, device xc3s200, package pq208, speed -4Loading device for application Par from file '3s200.nph' in environmentC:/Xilinx.Device speed data version:  PREVIEW 1.26 2003-06-19.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary:   Number of External IOBs            24 out of 141    17%      Number of LOCed External IOBs    0 out of 24      0%   Number of SLICELs                  14 out of 1920    1%   Number of SLICEMs                   8 out of 960     1%   Number of BUFGMUXs                  2 out of 8      25%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:98973f) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8..Phase 5.8 (Checksum:98ef8f) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file fifo2.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 218 unrouted;       REAL time: 0 secs Phase 2: 196 unrouted;       REAL time: 0 secs Phase 3: 55 unrouted;       REAL time: 0 secs Phase 4: 0 unrouted;       REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics.**************************Generating Clock Report**************************+-------------------------+----------+------+------+------------+-------------+|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+-------------------------+----------+------+------+------------+-------------+|        rclk_BUFGP       |  BUFGMUX0| No   |    5 |  0.007     |  0.366      |+-------------------------+----------+------+------+------------+-------------+|        wclk_BUFGP       |  BUFGMUX1| No   |   15 |  0.039     |  0.386      |+-------------------------+----------+------+------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  58 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file fifo2.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Sat Aug 02 12:56:25 2008--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module fifo2 . . .
PAR command line: par -w -intstyle ise -ol std -t 1 fifo2_map.ncd fifo2.ncd fifo2.pcf
PAR completed successfully