Release 6.1i Map G.23Xilinx Mapping Report File for Design 'fifo2'Design Information------------------Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s200-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o fifo2_map.ncd fifo2.ngd fifo2.pcf Target Device  : x3s200Target Package : pq208Target Speed   : -4Mapper Version : spartan3 -- $Revision: 1.16 $Mapped Date    : Sat Aug 02 12:56:23 2008Design Summary--------------Number of errors:      0Number of warnings:    8Logic Utilization:  Number of Slice Flip Flops:          21 out of   3,840    1%  Number of 4 input LUTs:              27 out of   3,840    1%Logic Distribution:  Number of occupied Slices:                           22 out of   1,920    1%    Number of Slices containing only related logic:      22 out of      22  100%    Number of Slices containing unrelated logic:          0 out of      22    0%      *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:             43 out of   3,840    1%  Number used as logic:                 27  Number used for Dual Port RAMs:       16    (Two LUTs used per Dual Port RAM)  Number of bonded IOBs:               24 out of     141   17%  Number of GCLKs:                     2 out of       8   25%Total equivalent gate count for design:  1,360Additional JTAG gate count for IOBs:  1,152Peak Memory Usage:  69 MBNOTES:   Related logic is defined as being logic that shares connectivity -   e.g. two LUTs are "related" if they share common inputs.   When assembling slices, Map gives priority to combine logic that   is related.  Doing so results in the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin   packing unrelated logic into a slice once 99% of the slices are   occupied through related logic packing.   Note that once logic distribution reaches the 99% level through   related logic packing, this does not mean the device is completely   utilized.  Unrelated logic packing will then begin, continuing until   all usable LUTs and FFs are occupied.  Depending on your timing   budget, increased levels of unrelated logic packing may adversely   affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_0_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_1_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_2_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_3_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_4_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_5_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_6_OBUF
   is configured, but output is not used.WARNING:DesignRules:331 - Blockcheck: Dangling G output. G of comp rdata_7_OBUF
   is configured, but output is not used.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:   BUFGP symbol "rclk_BUFGP" (output signal=rclk_BUFGP),   BUFGP symbol "wclk_BUFGP" (output signal=wclk_BUFGP)Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| rclk                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || rdata<0>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<1>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<2>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<3>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<4>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<5>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<6>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rdata<7>                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rempty                             | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || rinc                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || rrst_n                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wclk                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<0>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<1>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<2>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<3>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<4>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<5>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<6>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wdata<7>                           | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wfull                              | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       || winc                               | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       || wrst_n                             | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.