# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		an_dcfifo_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP3SE50F484C2
set_global_assignment -name FAMILY "Stratix III"
set_global_assignment -name TOP_LEVEL_ENTITY an_dcfifo_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:36:04  SEPTEMBER 06, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 8.0
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH my_tb -section_id eda_simulation
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_NAME my_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id my_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME an_dcfifo_top_vlg_vec_tst -section_id my_tb
set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/an_dcfifo_top.vt -section_id my_tb
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name USER_LIBRARIES "simulation/modelsim/;simulation/modelsim/;simulation/modelsim/;simulation/modelsim/;simulation/modelsim/"
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE an_dcfifo_top_fast_to_slow.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE an_dcfifo_top_fast_to_slow.vwf
set_global_assignment -name VERILOG_FILE read_control_logic.v
set_global_assignment -name HEX_FILE myrom.hex
set_global_assignment -name VERILOG_FILE write_control_logic.v
set_global_assignment -name VERILOG_FILE an_dcfifo_top.v
set_global_assignment -name VERILOG_FILE dcfifo8X32.v
set_global_assignment -name VERILOG_FILE ram256X32.v
set_global_assignment -name VERILOG_FILE rom256X32.v
set_global_assignment -name SDC_FILE an_dcfifo_top_fast_to_slow.sdc