ADC0809 VHDL控制程序
--文件名：ADC0809.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ADC0809 is
port ( d : in std_logic_vector(7 downto 0); --ADC0809輸出的采樣數(shù)據(jù)
clk,eoc : in std_logic; --clk為系統(tǒng)時鐘，eoc為ADC0809轉(zhuǎn)換結(jié)束信號
clk1,start, ale,en: out std_logic; --ADC0809控制信號
abc_in :in std_logic_vector(2 downto 0); --模擬選通信號
abc_out :out std_logic_vector(2 downto 0); --ADC0809模擬信號選通信號
q : out std_logic_vector(7 downto 0)); --送至8個并排數(shù)碼管信號
end ADC0809; 
architecture behav of ADC0809 is 
type states is ( st0,st1, st2, st3, st4,st5,st6); --定義各狀態(tài)的子類型
signal current_state, next_state:states:=st0;
signal regl :std_logic_vector(7 downto 0); --中間數(shù)據(jù)寄存信號
signal qq:std_logic_vector(7 downto 0);
begin
com:process(current_state,eoc) --規(guī)定各種狀態(tài)的轉(zhuǎn)換方式
begin
case current_state is
when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
when st3=> ale<='0';start<='0';en<='0';
if eoc='1' then next_state<=st3; --檢測EOC的下降沿
else next_state<=st4;
end if; 
when st4=> ale<='0';start<='0';en<='0';
if eoc='0' then next_state<=st4; --檢測EOC的上升沿
else next_state<=st5;
end if;
when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
when others=> next_state<=st0;ale<='0';start<='0';en<='0';
end case;
end process;
clock:process(clk) --對系統(tǒng)時鐘進行分頻，得到ADC0809轉(zhuǎn)換工作時鐘
begin
if clk'event and clk='1' then qq<=qq+1; --在clk1的上升沿，轉(zhuǎn)換至下一狀態(tài)
if QQ="01111111" THEN clk1<='1'; current_state <=next_state; 
elsif qq<="01111111" then clk1<='0'; 
end if; 
end if;
end process;
q<=regl; abc_out<=abc_in; 
end behav;