<!--
This XML file (created on Wed May 07 12:47:28 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>0015c563ebaf</host_id>
	<nic_id>001302a85905</nic_id>
	<cdrive_id>6c0f603a</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Wed May 07 12:47:28 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1596</cpu_freq>
	</cpu>
	<ram units="MB">503</ram>
</machine>
<top_file>D:/shujucaiji/shujucaiji</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off shujucaiji -c shujucaiji --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Circuit may not operate. Detected 49 non-operational path(s) clocked by clock &quot;clk&quot; with clock skew larger than data delay. See Compilation Report for details.</warning>
	<warning>Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Wed May 07 12:47:28 2008</info>
	<info>Info: th for memory &quot;ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated|ram_block1a7~porta_we_reg&quot; (data pin = &quot;wren&quot;, clock pin = &quot;clk&quot;) is 2.555 ns</info>
	<info>Info: - Shortest pin to memory delay is 7.881 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>wren</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>4.724 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>20.195 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>7.291 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>2.555 ns</actual>
	</nonclk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>136.82 MHz ( period = 7.309 ns )</actual>
	</clk>
	<clk>
		<name>wren</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>197.01 MHz ( period = 5.076 ns )</actual>
	</clk>
</performance>
<compile_id>53F123EE</compile_id>
</talkback>