library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10b is 
port(lock0,clr,clk,we:in std_logic;
     dout:out std_logic_vector(8 downto 0);
     clkout:out std_logic
    );
end cnt10b;
architecture one1 of cnt10b is 
signal cqi:std_logic_vector(8 downto 0);
signal clk0:std_logic;
begin 
clk0<=lock0 when we='1' else clk;
process(clk0,clr,cqi)
begin
if clr='1' then cqi<="000000000";
elsif clk0'event and clk0='1' then cqi<=cqi+1;
end if;
end process;
dout<=cqi;
clkout<=clk0;
end one1;