; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                        ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                        ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                   ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                   ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                   ;
; CBXI_PARAMETER         ; cntr_73e    ; Untyped                                                   ;
+------------------------+-------------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ram8b:inst2|altsyncram:altsyncram_component ;
+------------------------------------+-----------------+-----------------------------------+
; Parameter Name                     ; Value           ; Type                              ;
+------------------------------------+-----------------+-----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                           ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                    ;
; OPERATION_MODE                     ; SINGLE_PORT     ; Untyped                           ;
; WIDTH_A                            ; 8               ; Integer                           ;
; WIDTHAD_A                          ; 9               ; Integer                           ;
; NUMWORDS_A                         ; 512             ; Integer                           ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                           ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                           ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                           ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                           ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                           ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                           ;
; WIDTH_B                            ; 1               ; Untyped                           ;
; WIDTHAD_B                          ; 1               ; Untyped                           ;
; NUMWORDS_B                         ; 1               ; Untyped                           ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                           ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                           ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                           ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                           ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                           ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                           ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                           ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                           ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                           ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                           ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                           ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                           ;
; WIDTH_BYTEENA_A                    ; 1               ; Integer                           ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                           ;
; RAM_BLOCK_TYPE                     ; M4K             ; Untyped                           ;
; BYTE_SIZE                          ; 8               ; Untyped                           ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                           ;
; INIT_FILE                          ; UNUSED          ; Untyped                           ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                           ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                           ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                           ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                           ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                           ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                           ;
; DEVICE_FAMILY                      ; Cyclone         ; Untyped                           ;
; CBXI_PARAMETER                     ; altsyncram_gn51 ; Untyped                           ;
+------------------------------------+-----------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/shujucaiji/shujucaiji.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Wed May 07 12:47:09 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off shujucaiji -c shujucaiji
Info: Found 1 design units, including 1 entities, in source file shujucaiji.bdf
    Info: Found entity 1: shujucaiji
Info: Elaborating entity "shujucaiji" for the top level hierarchy
Warning: Using design file adcint.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: adcint-behav
    Info: Found entity 1: adcint
Info: Elaborating entity "adcint" for hierarchy "adcint:inst"
Info (10425): VHDL Case Statement information at adcint.vhd(34): OTHERS choice is never selected
Warning: Using design file cnt10b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: cnt10b-one1
    Info: Found entity 1: cnt10b
Info: Elaborating entity "cnt10b" for hierarchy "cnt10b:inst1"
Warning: Using design file lpm_conter8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_conter8-SYN
    Info: Found entity 1: lpm_conter8
Info: Elaborating entity "lpm_conter8" for hierarchy "lpm_conter8:inst3"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_conter8:inst3|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_73e.tdf
    Info: Found entity 1: cntr_73e
Info: Elaborating entity "cntr_73e" for hierarchy "lpm_conter8:inst3|lpm_counter:lpm_counter_component|cntr_73e:auto_generated"
Warning: Using design file ram8b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ram8b-SYN
    Info: Found entity 1: ram8b
Info: Elaborating entity "ram8b" for hierarchy "ram8b:inst2"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "ram8b:inst2|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gn51.tdf
    Info: Found entity 1: altsyncram_gn51
Info: Elaborating entity "altsyncram_gn51" for hierarchy "ram8b:inst2|altsyncram:altsyncram_component|altsyncram_gn51:auto_generated"
Info: State machine "|shujucaiji|adcint:inst|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|shujucaiji|adcint:inst|current_state"
Info: Encoding result for state machine "|shujucaiji|adcint:inst|current_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "adcint:inst|current_state.st4"
        Info: Encoded state bit "adcint:inst|current_state.st3"
        Info: Encoded state bit "adcint:inst|current_state.st2"
        Info: Encoded state bit "adcint:inst|current_state.st1"
        Info: Encoded state bit "adcint:inst|current_state.st0"
    Info: State "|shujucaiji|adcint:inst|current_state.st0" uses code string "00000"
    Info: State "|shujucaiji|adcint:inst|current_state.st1" uses code string "00011"
    Info: State "|shujucaiji|adcint:inst|current_state.st2" uses code string "00101"
    Info: State "|shujucaiji|adcint:inst|current_state.st3" uses code string "01001"
    Info: State "|shujucaiji|adcint:inst|current_state.st4" uses code string "10001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "adda" stuck at VCC
Info: Implemented 83 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 31 output pins
    Info: Implemented 32 logic cells
    Info: Implemented 8 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Wed May 07 12:47:13 2008
    Info: Elapsed time: 00:00:04