{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_73e lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated " "Info: Elaborating entity \"cntr_73e\" for hierarchy \"lpm_conter8:inst3\|lpm_counter:lpm_counter_component\|cntr_73e:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ram8b.vhd 2 1 " "Warning: Using design file ram8b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram8b-SYN " "Info: Found design unit 1: ram8b-SYN" {  } { { "ram8b.vhd" "" { Text "D:/shujucaiji/ram8b.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ram8b " "Info: Found entity 1: ram8b" {  } { { "ram8b.vhd" "" { Text "D:/shujucaiji/ram8b.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram8b ram8b:inst2 " "Info: Elaborating entity \"ram8b\" for hierarchy \"ram8b:inst2\"" {  } { { "shujucaiji.bdf" "inst2" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 192 544 704 304 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ram8b:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ram8b:inst2\|altsyncram:altsyncram_component\"" {  } { { "ram8b.vhd" "altsyncram_component" { Text "D:/shujucaiji/ram8b.vhd" 87 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gn51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gn51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gn51 " "Info: Found entity 1: altsyncram_gn51" {  } { { "db/altsyncram_gn51.tdf" "" { Text "D:/shujucaiji/db/altsyncram_gn51.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gn51 ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated " "Info: Elaborating entity \"altsyncram_gn51\" for hierarchy \"ram8b:inst2\|altsyncram:altsyncram_component\|altsyncram_gn51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus51/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|shujucaiji\|adcint:inst\|current_state 5 " "Info: State machine \"\|shujucaiji\|adcint:inst\|current_state\" contains 5 states" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|shujucaiji\|adcint:inst\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|shujucaiji\|adcint:inst\|current_state\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|shujucaiji\|adcint:inst\|current_state " "Info: Encoding result for state machine \"\|shujucaiji\|adcint:inst\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "adcint:inst\|current_state.st4 " "Info: Encoded state bit \"adcint:inst\|current_state.st4\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "adcint:inst\|current_state.st3 " "Info: Encoded state bit \"adcint:inst\|current_state.st3\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "adcint:inst\|current_state.st2 " "Info: Encoded state bit \"adcint:inst\|current_state.st2\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "adcint:inst\|current_state.st1 " "Info: Encoded state bit \"adcint:inst\|current_state.st1\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "adcint:inst\|current_state.st0 " "Info: Encoded state bit \"adcint:inst\|current_state.st0\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shujucaiji\|adcint:inst\|current_state.st0 00000 " "Info: State \"\|shujucaiji\|adcint:inst\|current_state.st0\" uses code string \"00000\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shujucaiji\|adcint:inst\|current_state.st1 00011 " "Info: State \"\|shujucaiji\|adcint:inst\|current_state.st1\" uses code string \"00011\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shujucaiji\|adcint:inst\|current_state.st2 00101 " "Info: State \"\|shujucaiji\|adcint:inst\|current_state.st2\" uses code string \"00101\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shujucaiji\|adcint:inst\|current_state.st3 01001 " "Info: State \"\|shujucaiji\|adcint:inst\|current_state.st3\" uses code string \"01001\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|shujucaiji\|adcint:inst\|current_state.st4 10001 " "Info: State \"\|shujucaiji\|adcint:inst\|current_state.st4\" uses code string \"10001\"" {  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 39 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "adcint.vhd" "" { Text "D:/shujucaiji/adcint.vhd" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "adda VCC " "Warning: Pin \"adda\" stuck at VCC" {  } { { "shujucaiji.bdf" "" { Schematic "D:/shujucaiji/shujucaiji.bdf" { { 152 776 952 168 "adda" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "83 " "Info: Implemented 83 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "31 " "Info: Implemented 31 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "32 " "Info: Implemented 32 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 07 12:47:13 2008 " "Info: Processing ended: Wed May 07 12:47:13 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}