library IEEE;use IEEE.Std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;entity CFIFO is   generic(m, n : Positive := 4); --m is depth, n is width   port(RST,CLK,WRREQ, RDREQ : in Std_logic;         DATAIN : in Std_logic_vector((n-1) downto 0);         DATAOUT : out Std_logic_vector((n-1) downto 0);         FULL, EMPTY : out Std_logic);end CFIFO;architecture V2 of CFIFO is   type FIFOM is array(0 to (m-1)) of Std_logic_vector((n-1) downto 0);   signal CFIFO_memory : FIFOM;   signal Wraddr, Rdaddr, Offset : Natural range 0 to (m-1);   signal Rdpulse, Wrpulse, Q1, Q2, Q3, Q4,FI,EI : Std_logic;   signal Databuffer : Std_logic_vector((n-1) downto 0);begin	CFIFO_write : process	begin		  wait until rising_edge(CLK);		  if RST = '1' then  Wraddr <= 0;		  elsif (Wrpulse = '1' and FI = '0') then			 CFIFO_memory(Wraddr) <= DATAIN;			 Wraddr <= (Wraddr + 1) mod m;----Natural		  end if;	end process;
	
	CFIFO_read : process	begin		  wait until rising_edge(CLK);		  if RST='1' then Rdaddr <= 0;  Databuffer<= (others => '0');		  elsif (Rdpulse = '1' and EI = '0') then			 Databuffer<=CFIFO_memory(Rdaddr);  Rdaddr<=(Rdaddr+1) mod m;		  end if;	end process;
		   	sync_ffs : process    begin			wait until rising_edge(CLK);			Q1 <= WRREQ;		Q2 <= Q1;---1			Q3 <= RDREQ;		Q4 <= Q3;--1	end process;
	Wrpulse <= Q2 and not(Q1);	Rdpulse <= Q4 and not(Q3);   Offset <= (Wraddr - Rdaddr) when (Wraddr > Rdaddr)             else (m - (Rdaddr - Wraddr)) when (Rdaddr > Wraddr)            else 0; EI<= '1' when (Offset = 0) else '0'; FI<= '1' when (Offset = (m-1)) else '0';EMPTY<=EI;
FULL<=FI;
DATAOUT <= Databuffer when RDREQ = '0'             else (others => 'Z');end V2;