?? mlt.tan.rpt
字號:
Timing Analyzer report for mlt
Sat Feb 18 13:52:05 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.745 ns ; a[1] ; c[6] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 9.745 ns ; a[1] ; c[6] ;
; N/A ; None ; 9.713 ns ; a[1] ; c[1] ;
; N/A ; None ; 9.696 ns ; a[1] ; c[2] ;
; N/A ; None ; 9.587 ns ; b[0] ; c[6] ;
; N/A ; None ; 9.585 ns ; b[1] ; c[7] ;
; N/A ; None ; 9.547 ns ; b[1] ; c[5] ;
; N/A ; None ; 9.475 ns ; b[1] ; c[1] ;
; N/A ; None ; 9.443 ns ; b[1] ; c[2] ;
; N/A ; None ; 9.398 ns ; a[0] ; c[7] ;
; N/A ; None ; 9.376 ns ; a[0] ; c[6] ;
; N/A ; None ; 9.367 ns ; a[0] ; c[5] ;
; N/A ; None ; 9.360 ns ; a[0] ; c[1] ;
; N/A ; None ; 9.345 ns ; a[0] ; c[2] ;
; N/A ; None ; 9.302 ns ; b[0] ; c[1] ;
; N/A ; None ; 9.280 ns ; b[0] ; c[2] ;
; N/A ; None ; 9.255 ns ; b[1] ; c[6] ;
; N/A ; None ; 9.240 ns ; a[1] ; c[7] ;
; N/A ; None ; 9.205 ns ; b[0] ; c[7] ;
; N/A ; None ; 9.202 ns ; a[1] ; c[5] ;
; N/A ; None ; 9.164 ns ; b[0] ; c[5] ;
; N/A ; None ; 9.139 ns ; b[0] ; c[4] ;
; N/A ; None ; 9.123 ns ; b[0] ; c[3] ;
; N/A ; None ; 9.027 ns ; a[1] ; c[4] ;
; N/A ; None ; 9.010 ns ; a[0] ; c[4] ;
; N/A ; None ; 9.010 ns ; a[1] ; c[3] ;
; N/A ; None ; 8.993 ns ; a[0] ; c[3] ;
; N/A ; None ; 8.799 ns ; b[1] ; c[4] ;
; N/A ; None ; 8.772 ns ; b[1] ; c[3] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 13:52:04 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[1]" to destination pin "c[6]" is 9.745 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'a[1]'
Info: 2: + IC(2.731 ns) + CELL(0.740 ns) = 4.603 ns; Loc. = LC_X16_Y2_N6; Fanout = 1; COMB Node = 'reduce_or~40'
Info: 3: + IC(2.820 ns) + CELL(2.322 ns) = 9.745 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'c[6]'
Info: Total cell delay = 4.194 ns ( 43.04 % )
Info: Total interconnect delay = 5.551 ns ( 56.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Feb 18 13:52:04 2006
Info: Elapsed time: 00:00:01
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