?? mlt.fit.rpt
字號(hào):
Fitter report for mlt
Sat Feb 18 13:51:58 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. I/O Bank Usage
11. All Package Pins
12. Output Pin Default Load For Reported TCO
13. Fitter Resource Utilization by Entity
14. Delay Chain Summary
15. Non-Global High Fan-Out Signals
16. Interconnect Usage Summary
17. LAB Logic Elements
18. LAB Signals Sourced
19. LAB Signals Sourced Out
20. LAB Distinct Inputs
21. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Sat Feb 18 13:51:58 2006 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; mlt ;
; Top-level Entity Name ; mlt ;
; Family ; MAX II ;
; Device ; EPM1270T144C5 ;
; Timing Models ; Final ;
; Total logic elements ; 7 / 1,270 ( < 1 % ) ;
; Total pins ; 20 / 116 ( 17 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
+-----------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------+--------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------+--------------------+--------------------------------+
; Device ; EPM1270T144C5 ; ;
; Optimize Hold Timing ; Off ; IO Paths and Minimum TPD Paths ;
; Fitter Effort ; Standard Fit ; Auto Fit ;
; Use smart compilation ; Off ; Off ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Fast-Corner Timing ; Off ; Off ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Delay Chains ; On ; On ;
; Perform Physical Synthesis for Combinational Logic ; Off ; Off ;
; Perform Register Duplication ; Off ; Off ;
; Perform Register Retiming ; Off ; Off ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
; Auto Register Duplication ; Off ; Off ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Always Enable Input Buffers ; Off ; Off ;
+--------------------------------------------------------+--------------------+--------------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/乘法器/mlt.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基礎(chǔ)實(shí)驗(yàn)/乘法器/mlt.pin.
+-------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+---------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------+
; Total logic elements ; 7 / 1,270 ( < 1 % ) ;
; -- Combinational with no register ; 7 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 0 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
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