-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L12 is d_tmp[0]~32
--operation mode is normal

A1L12 = a & b[0] # !a & (c[0]);


--A1L22 is d_tmp[1]~33
--operation mode is normal

A1L22 = a & b[1] # !a & (c[1]);


--A1L32 is d_tmp[2]~34
--operation mode is normal

A1L32 = a & b[2] # !a & (c[2]);


--A1L42 is d_tmp[3]~35
--operation mode is normal

A1L42 = a & b[3] # !a & (c[3]);


--A1L43 is reduce_or~35
--operation mode is normal

A1L43 = A1L12 & (A1L42 # A1L22 $ A1L32) # !A1L12 & (A1L22 # A1L32 $ A1L42);


--A1L53 is reduce_or~36
--operation mode is normal

A1L53 = A1L12 & (A1L42 $ (A1L22 # !A1L32)) # !A1L12 & A1L22 & !A1L32 & !A1L42;


--A1L63 is reduce_or~37
--operation mode is normal

A1L63 = A1L22 & A1L12 & (!A1L42) # !A1L22 & (A1L32 & (!A1L42) # !A1L32 & A1L12);


--A1L73 is reduce_or~38
--operation mode is normal

A1L73 = A1L12 & (A1L22 $ !A1L32) # !A1L12 & (A1L22 & !A1L32 & A1L42 # !A1L22 & A1L32 & !A1L42);


--A1L83 is reduce_or~39
--operation mode is normal

A1L83 = A1L32 & A1L42 & (A1L22 # !A1L12) # !A1L32 & !A1L12 & A1L22 & !A1L42;


--A1L93 is reduce_or~40
--operation mode is normal

A1L93 = A1L22 & (A1L12 & (A1L42) # !A1L12 & A1L32) # !A1L22 & A1L32 & (A1L12 $ A1L42);


--A1L04 is reduce_or~41
--operation mode is normal

A1L04 = A1L32 & !A1L22 & (A1L12 $ !A1L42) # !A1L32 & A1L12 & (A1L22 $ !A1L42);


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--c[0] is c[0]
--operation mode is input

c[0] = INPUT();


--a is a
--operation mode is input

a = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--c[1] is c[1]
--operation mode is input

c[1] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--c[2] is c[2]
--operation mode is input

c[2] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--c[3] is c[3]
--operation mode is input

c[3] = INPUT();


--d[0] is d[0]
--operation mode is output

d[0] = OUTPUT(VCC);


--d[1] is d[1]
--operation mode is output

d[1] = OUTPUT(!A1L43);


--d[2] is d[2]
--operation mode is output

d[2] = OUTPUT(A1L53);


--d[3] is d[3]
--operation mode is output

d[3] = OUTPUT(A1L63);


--d[4] is d[4]
--operation mode is output

d[4] = OUTPUT(A1L73);


--d[5] is d[5]
--operation mode is output

d[5] = OUTPUT(A1L83);


--d[6] is d[6]
--operation mode is output

d[6] = OUTPUT(A1L93);


--d[7] is d[7]
--operation mode is output

d[7] = OUTPUT(A1L04);


--en[0] is en[0]
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1]
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2]
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3]
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4]
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5]
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6]
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7]
--operation mode is output

en[7] = OUTPUT(VCC);