{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 29 23:04:25 2008 " "Info: Processing started: Wed Oct 29 23:04:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TOTAL -c TOTAL " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TOTAL -c TOTAL" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK_CHOOSE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLK_CHOOSE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLK_CHOOSE-BEHAV " "Info: Found design unit 1: CLK_CHOOSE-BEHAV" {  } { { "CLK_CHOOSE.vhd" "" { Text "J:/ALL/CLK_CHOOSE.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CLK_CHOOSE " "Info: Found entity 1: CLK_CHOOSE" {  } { { "CLK_CHOOSE.vhd" "" { Text "J:/ALL/CLK_CHOOSE.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DISPLAY-DISP_ARE " "Info: Found design unit 1: DISPLAY-DISP_ARE" {  } { { "display.vhd" "" { Text "J:/ALL/display.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DISPLAY " "Info: Found entity 1: DISPLAY" {  } { { "display.vhd" "" { Text "J:/ALL/display.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HOUR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file HOUR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HOUR-BEHAV " "Info: Found design unit 1: HOUR-BEHAV" {  } { { "HOUR.vhd" "" { Text "J:/ALL/HOUR.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 HOUR " "Info: Found entity 1: HOUR" {  } { { "HOUR.vhd" "" { Text "J:/ALL/HOUR.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MINUTE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file MINUTE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MINUTE-MIN " "Info: Found design unit 1: MINUTE-MIN" {  } { { "MINUTE.vhd" "" { Text "J:/ALL/MINUTE.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 MINUTE " "Info: Found entity 1: MINUTE" {  } { { "MINUTE.vhd" "" { Text "J:/ALL/MINUTE.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file second.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SECOND-SEC " "Info: Found design unit 1: SECOND-SEC" {  } { { "second.vhd" "" { Text "J:/ALL/second.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SECOND " "Info: Found entity 1: SECOND" {  } { { "second.vhd" "" { Text "J:/ALL/second.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seltime.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seltime.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SELTIME-FUN " "Info: Found design unit 1: SELTIME-FUN" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SELTIME " "Info: Found entity 1: SELTIME" {  } { { "seltime.vhd" "" { Text "J:/ALL/seltime.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TOTAL.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file TOTAL.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TOTAL " "Info: Found entity 1: TOTAL" {  } { { "TOTAL.bdf" "" { Schematic "J:/ALL/TOTAL.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TOTAL " "Info: Elaborating entity \"TOTAL\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "HOUR HOUR:inst3 " "Info: Elaborating entity \"HOUR\" for hierarchy \"HOUR:inst3\"" {  } { { "TOTAL.bdf" "inst3" { Schematic "J:/ALL/TOTAL.bdf" { { 240 328 488 336 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_CHOOSE CLK_CHOOSE:inst2 " "Info: Elaborating entity \"CLK_CHOOSE\" for hierarchy \"CLK_CHOOSE:inst2\"" {  } { { "TOTAL.bdf" "inst2" { Schematic "J:/ALL/TOTAL.bdf" { { 104 56 248 232 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SEC_COUT CLK_CHOOSE.vhd(28) " "Warning (10492): VHDL Process Statement warning at CLK_CHOOSE.vhd(28): signal \"SEC_COUT\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CLK_CHOOSE.vhd" "" { Text "J:/ALL/CLK_CHOOSE.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}