#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj
#-- Written on Fri Jun 30 17:01:13 2000


#add_file options
add_file -vhdl -lib work "d:/projects/altera/lpcores/ddr/release/vhdl/v1_0/source/ddr_control_interface.vhd"
add_file -vhdl -lib work "d:/projects/altera/lpcores/ddr/release/vhdl/v1_0/source/ddr_data_path.vhd"
add_file -vhdl -lib work "d:/projects/altera/lpcores/ddr/release/vhdl/v1_0/source/ddr_command.vhd"
add_file -vhdl -lib work "d:/projects/altera/lpcores/ddr/release/vhdl/v1_0/source/ddr_sdram.vhd"


#implementation: "rev_1"
impl -name rev_1

#device options
set_option -technology APEX20K
set_option -part EP20K400E
set_option -package FC672
set_option -speed_grade -1X

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 200.000
set_option -domap 1
set_option -disable_io_insertion 0
set_option -cliquing 1
set_option -pipe 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/ddr_sdram.vqm"