Fitter report for full_adder
Tue Jun 25 02:46:02 2002
Quartus II Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version


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; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Pad To Core Delay Chain Fanout
 14. Non-Global High Fan-Out Signals
 15. Interconnect Usage Summary
 16. LAB Logic Elements
 17. LAB Signals Sourced
 18. LAB Signals Sourced Out
 19. LAB Distinct Inputs
 20. Fitter Device Options
 21. Operating Settings and Conditions
 22. Fitter Messages
 23. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Tue Jun 25 02:46:02 2002         ;
; Quartus II Version                 ; 7.2 Build 203 02/05/2008 SP 2 SJ Full Version ;
; Revision Name                      ; full_adder                                    ;
; Top-level Entity Name              ; full_adder                                    ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C35F672C6                                  ;
; Timing Models                      ; Final                                         ;
; Total logic elements               ; 2 / 33,216 ( < 1 % )                          ;
;     Total combinational functions  ; 2 / 33,216 ( < 1 % )                          ;
;     Dedicated logic registers      ; 0 / 33,216 ( 0 % )                            ;
; Total registers                    ; 0                                             ;
; Total pins                         ; 8 / 475 ( 2 % )                               ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                           ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                                ;
; Total PLLs                         ; 0 / 4 ( 0 % )                                 ;
+------------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C35F672C6                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;