?? full_adder.fit.rpt
字號:
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; PCI I/O ; Off ; Off ;
; Weak Pull-Up Resistor ; Off ; Off ;
; Enable Bus-Hold Circuitry ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto ; Auto ;
; Auto Delay Chains ; On ; On ;
; Auto Merge PLLs ; On ; On ;
; Ignore PLL Mode When Merging PLLs ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
; Perform Register Duplication for Performance ; Off ; Off ;
; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
; Perform Register Retiming for Performance ; Off ; Off ;
; Perform Asynchronous Signal Pipelining ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Physical Synthesis Effort Level ; Normal ; Normal ;
; Auto Global Clock ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Stop After Congestion Map Generation ; Off ; Off ;
; Save Intermediate Fitting Results ; Off ; Off ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in d:/jinguiyu/full_adder.pin.
+--------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+---------------------------------------------+----------------------+
; Resource ; Usage ;
+---------------------------------------------+----------------------+
; Total logic elements ; 2 / 33,216 ( < 1 % ) ;
; -- Combinational with no register ; 2 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 0 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 2 ;
; -- <=2 input functions ; 0 ;
; -- Register only ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 2 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers* ; 0 / 34,593 ( 0 % ) ;
; -- Dedicated logic registers ; 0 / 33,216 ( 0 % ) ;
; -- I/O registers ; 0 / 1,377 ( 0 % ) ;
; ; ;
; Total LABs: partially or completely used ; 1 / 2,076 ( < 1 % ) ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; I/O pins ; 8 / 475 ( 2 % ) ;
; -- Clock pins ; 1 / 8 ( 13 % ) ;
; Global signals ; 0 ;
; M4Ks ; 0 / 105 ( 0 % ) ;
; Total memory bits ; 0 / 483,840 ( 0 % ) ;
; Total RAM block bits ; 0 / 483,840 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % ) ;
; PLLs ; 0 / 4 ( 0 % ) ;
; Global clocks ; 0 / 16 ( 0 % ) ;
; Average interconnect usage ; 0% ;
; Peak interconnect usage ; 0% ;
; Maximum fan-out node ; ain ;
; Maximum fan-out ; 3 ;
; Highest non-global fan-out signal ; ain ;
; Highest non-global fan-out ; 3 ;
; Total fan-out ; 11 ;
; Average fan-out ; 0.85 ;
+---------------------------------------------+----------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; ain ; C13 ; 3 ; 31 ; 36 ; 2 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; bin ; J10 ; 3 ; 27 ; 36 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
; cin ; D13 ; 3 ; 31 ; 36 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; cout ; C11 ; 3 ; 29 ; 36 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;
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