`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:21:43 2006				
// Last Change  :   Thu Nov  2 12:21:43 2006			
// Module Name  :   alu_mux					
// Filename     :   alu_mux.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module alu_mux (
		alu_arith_res,
		cy_arith_res,
		alu_shft_res,
		cy_shft_res,
		sel_func,
		reg_cy_bus,
		reg_alu_bus
);

	input	[7:0]	alu_arith_res;
	input		cy_arith_res;
	input	[7:0]	alu_shft_res;
	input		cy_shft_res;
	input		sel_func;

	output		reg_cy_bus;
	output	[7:0]	reg_alu_bus;

	reg		reg_cy_bus;
	reg	[7:0]	reg_alu_bus;

	parameter ARITH =	1'b0;
	parameter SHFT =	1'b1;

	always @(alu_arith_res or cy_arith_res or
		 alu_shft_res or cy_shft_res or
		 sel_func)
	begin
		case (sel_func)
		ARITH:
			begin
				reg_cy_bus = cy_arith_res;
				reg_alu_bus [7:0] = alu_arith_res[7:0];
			end
		SHFT:
			begin
				reg_cy_bus = cy_shft_res;
				reg_alu_bus [7:0] = alu_shft_res[7:0];
			end
		default:
			begin
				reg_cy_bus = 1'b0;
				reg_alu_bus [7:0] = 8'h00;
			end
		endcase
	end

endmodule