`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:51:10 2006				
// Last Change  :   Thu Nov  2 12:51:10 2006			
// Module Name  :   mini_core					
// Filename     :   tb_mini_core.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module tb_mini_core (
);

  ///////////////////////////////////////////////
  //// Template for clk and reset generation ////
  //// uncomment it when needed              ////
  /////////////////////////////////////////////// 
  parameter CLKPERIODE = 100;

  reg clk;
  reg a_reset_l;
 
  initial clk = 1'b1;
  always #(CLKPERIODE/2) clk = !clk;

  initial begin
      a_reset_l = 1'b0;
      #33
      a_reset_l = 1'b1;
  end 
  /////////////////////////////////////////////// 

	reg	[7:0]	data_in;
	reg	[2:0]	instr;
	wire 	[7:0]	data_out;
	
	parameter I_MOV_IN_TO_ACC       = 3'b001;
	parameter I_ADD_IN_TO_ACC       = 3'b010;
	parameter I_SHIFT_ACC           = 3'b011;
	parameter I_MOV_IN_TO_ADR       = 3'b100;
	parameter I_MOV_IN_TO_RAM       = 3'b101;
	parameter I_MOV_RAM_TO_ACC      = 3'b110;


  mini_core mini_core_i (
	.clk(clk),
	.a_reset_l(a_reset_l),
	.data_in(data_in),
	.instr(instr),
	.data_out(data_out)
		);
	
  // Template for testcase specific pattern generation
  // File has to be situated in simulation/[testcase] directory

`include "testcase.v"
//Fill in testcase specific pattern generation
endmodule