`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:30:11 2006				
// Last Change  :   Thu Nov  2 12:30:11 2006			
// Module Name  :   mini_core_2					
// Filename     :   mini_core_2.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module mini_core (
	clk,
	a_reset_l,
	data_in,
	instr,
	data_out
);
	input		clk;
	input		a_reset_l;
	input	[7:0]	data_in;
	input	[2:0]	instr;

	output 	[7:0]	data_out;

	wire	[1:0]	data_sel;
	wire		sel_acc;
	wire		sel_cy;
	wire		sel_opa;
	wire	[1:0]	sel_opb;
	wire		sel_ram_adr;
	wire		sel_func;
	wire		ram_cen;
	wire		ram_wen;
	wire		ram_oen;

dat dat_i(
	.clk(clk),
	.a_reset_l(a_reset_l),
	.data_in(data_in),
	.data_sel(data_sel),
	.sel_acc(sel_acc),
	.sel_cy(sel_cy),
	.sel_opa(sel_opa),
	.sel_opb(sel_opb),
	.sel_ram_adr(sel_ram_adr),
	.sel_func(sel_func),
	.ram_cen(ram_cen),
	.ram_wen(ram_wen),
	.ram_oen(ram_oen),
	.data_out(data_out)
);

ctrl ctrl_i(
	.clk(clk),
	.a_reset_l(a_reset_l),
	.instr(instr),
	.data_sel(data_sel),
	.sel_acc(sel_acc),
	.sel_cy(sel_cy),
	.sel_opa(sel_opa),
	.sel_opb(sel_opb),
	.sel_ram_adr(sel_ram_adr),
	.sel_func(sel_func),
	.ram_cen(ram_cen),
	.ram_wen(ram_wen),
	.ram_oen(ram_oen)
);

endmodule