`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:25:09 2006				
// Last Change  :   Thu Nov  2 12:25:09 2006			
// Module Name  :   dat_alu					
// Filename     :   dat_alu.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module dat_alu (
	reg_alu_opa_bus,
	reg_alu_opb_bus,
	sel_func,
	reg_cy,
	reg_cy_bus,
	reg_alu_bus
);

	input	[7:0]	reg_alu_opa_bus;
	input	[7:0]	reg_alu_opb_bus;
	input		sel_func;
	input		reg_cy;

	output		reg_cy_bus;
	output	[7:0]	reg_alu_bus;

	wire	[7:0]	reg_alu_opa_bus;
	wire	[7:0]	reg_alu_opb_bus;
	wire		sel_func;
	wire		reg_cy;
	wire		reg_cy_bus;
	wire	[7:0]	reg_alu_bus;

	wire	[7:0]	alu_arith_res;
	wire		cy_arith_res;
	wire	[7:0]	alu_shft_res;
	wire		cy_shft_res;

  alu_arith alu_arith_i (
		.reg_alu_opa_bus(reg_alu_opa_bus),
		.reg_alu_opb_bus(reg_alu_opb_bus),
		.reg_cy(reg_cy),
		.alu_arith_res(alu_arith_res),
		.cy_arith_res(cy_arith_res)
		);

  alu_shft alu_shft_i (
		.reg_alu_opb_bus(reg_alu_opb_bus),
		.reg_cy(reg_cy),
		.alu_shft_res(alu_shft_res),
		.cy_shft_res(cy_shft_res)
		);

  alu_mux alu_mux_i (
		.alu_arith_res(alu_arith_res),
		.cy_arith_res(cy_arith_res),
		.alu_shft_res(alu_shft_res),
		.cy_shft_res(cy_shft_res),
		.sel_func(sel_func),
		.reg_cy_bus(reg_cy_bus),
		.reg_alu_bus(reg_alu_bus)
		);

endmodule