`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:26:00 2006				
// Last Change  :   Thu Nov  2 12:26:00 2006			
// Module Name  :   dat_mx_bus					
// Filename     :   dat_mx_bus.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module dat_mx_bus (
	data_in,
	reg_acc_bus,
	reg_alu_bus,
	ram_in,
	data_sel,
	data_bus
);

	input	[7:0]	data_in;
	input	[7:0]	reg_acc_bus;
	input	[7:0]	reg_alu_bus;
	input	[7:0]	ram_in;

	input	[1:0]	data_sel;

	output	[7:0]	data_bus;

	reg	[7:0]	data_bus;

	parameter SEL_IN =	2'b00;
	parameter SEL_ACC =	2'b01;
	parameter SEL_ALU =	2'b10;
	parameter SEL_RAM =	2'b11;

	always @(data_in or reg_acc_bus or reg_alu_bus or data_sel or ram_in)
	begin
		case (data_sel)
		SEL_IN:
			begin
				data_bus [7:0] = data_in[7:0];
			end
		SEL_ACC:
			begin
				data_bus [7:0] = reg_acc_bus[7:0];
			end
		SEL_ALU:
			begin
				data_bus [7:0] = reg_alu_bus[7:0];
			end
		SEL_RAM:
			begin
				data_bus [7:0] = ram_in[7:0];
			end
		default:
			begin
				data_bus [7:0] = 8'h00;
			end
		endcase
	end

endmodule