`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:20:21 2006				
// Last Change  :   Thu Nov  2 12:20:21 2006			
// Module Name  :   alu_arith					
// Filename     :   alu_arith.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module alu_arith (
		reg_alu_opa_bus,
		reg_alu_opb_bus,
		reg_cy,
		alu_arith_res,
		cy_arith_res
);

	input	[7:0]	reg_alu_opa_bus;
	input	[7:0]	reg_alu_opb_bus;
	input		reg_cy;

	output	[7:0]	alu_arith_res;
	output		cy_arith_res;

	reg	[7:0]	alu_arith_res;
	reg		cy_arith_res;

	always @(reg_alu_opa_bus or reg_alu_opb_bus or reg_cy)
	begin
		{cy_arith_res, alu_arith_res[7:0]} =
			reg_alu_opa_bus[7:0] + reg_alu_opb_bus[7:0] + {7'b0000000, reg_cy};
	end

endmodule