`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:28:48 2006				
// Last Change  :   Thu Nov  2 12:28:48 2006			
// Module Name  :   dat_reg					
// Filename     :   dat_reg.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module dat_reg (
	clk,
	a_reset_l,
	data_bus,
	sel_acc,
	sel_cy,
	sel_opa,
	sel_opb,
	sel_ram_adr,
	reg_cy_bus,
	reg_cy,
	reg_acc_bus,
	reg_alu_opa_bus,
	reg_alu_opb_bus,
	reg_ram_adr
);

  	input		clk;
	input		a_reset_l;
	input	[7:0]	data_bus;
	input		sel_acc;
	input		sel_cy;
	input		sel_opa;
	input	[1:0]	sel_opb;
	input		sel_ram_adr;
	input		reg_cy_bus;

	output		reg_cy;
	output	[7:0]	reg_acc_bus;
	output	[7:0]	reg_alu_opa_bus;
	output	[7:0]	reg_alu_opb_bus;
	output	[6:0]	reg_ram_adr;

	reg	[7:0]	reg_acc;
	reg	[7:0]	reg_opa;
	reg	[7:0]	reg_opb;
	reg	[6:0]	reg_ram_adr;
	reg		reg_cy;

	always @(posedge clk or negedge a_reset_l)
	begin
		if (a_reset_l == 1'b0)
		begin
			reg_acc <= 8'h00;
			reg_opa <= 8'h00;
			reg_opb <= 8'h00;
			reg_ram_adr <= 7'h00;
			reg_cy <= 1'b0;
		end
		else
		begin
			if (sel_acc == 1'b1)
			begin
				reg_acc[7:0] <= data_bus[7:0];
			end

			if (sel_opa == 1'b1)
			begin
				reg_opa[7:0] <= data_bus[7:0];
			end

			if (sel_opb == 2'b01)
			begin
				reg_opb[7:0] <= data_bus[7:0];
			end

			if (sel_opb == 2'b10)
			begin
				reg_opb[7:0] <= reg_acc[7:0];
			end

			if (sel_ram_adr == 1'b1)
			begin
				reg_ram_adr[6:0] <= data_bus[6:0];
			end

			if (sel_cy == 1'b1)
			begin
				reg_cy <= reg_cy_bus;
			end
		end
	end

	assign reg_acc_bus = reg_acc;
	assign reg_alu_opa_bus = reg_opa;
	assign reg_alu_opb_bus = reg_opb;

endmodule