`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:23:14 2006				
// Last Change  :   Thu Nov  2 12:23:14 2006			
// Module Name  :   ctrl					
// Filename     :   ctrl.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module ctrl (
	clk,
	a_reset_l,
	instr,
	data_sel,
	sel_acc,
	sel_cy,
	sel_opa,
	sel_opb,
	sel_ram_adr,
	sel_func,
	ram_cen,
	ram_wen,
	ram_oen
);

	input		clk;
	input		a_reset_l;
	input	[2:0]	instr;

	output	[1:0]	data_sel;
	output		sel_acc;
	output		sel_cy;
	output		sel_opa;
	output	[1:0]	sel_opb;
	output		sel_ram_adr;
	output		sel_func;
	output		ram_cen;
	output		ram_wen;
	output		ram_oen;

	reg	[1:0]	data_sel;
	reg		sel_acc;
	reg		sel_cy;
	reg		sel_opa;
	reg	[1:0]	sel_opb;
	reg		sel_ram_adr;
	reg		sel_func;
	reg		ram_cen;
	reg		ram_wen;
	reg		ram_oen;

	reg	[3:0]	current_state;
	reg	[3:0]	next_state;
	
	parameter I_MOV_IN_TO_ACC       = 3'b001;
	parameter I_ADD_IN_TO_ACC       = 3'b010;
	parameter I_SHIFT_ACC           = 3'b011;
	parameter I_MOV_IN_TO_ADR       = 3'b100;
	parameter I_MOV_IN_TO_RAM       = 3'b101;
	parameter I_MOV_RAM_TO_ACC      = 3'b110;

	parameter S_READY_FOR_INSTR     = 4'b0000;
	parameter S_I2A	                = 4'b0001;
	parameter S_I2OPA_A2OPB         = 4'b0010;
	parameter S_ADD_AB2A            = 4'b0011;
	parameter S_A2OPB               = 4'b0100;
	parameter S_SH_OPB2A            = 4'b0101;

	parameter S_I2ADR               = 4'b0110;
	parameter S_I2RAM               = 4'b0111;
	parameter S_RAM2A               = 4'b1000;
	parameter S_RAM2AB              = 4'b1001;


	always @(posedge clk or negedge a_reset_l)
	begin
		if (a_reset_l == 1'b0)
		begin
			current_state <= 4'h0;
		end
		else
		begin
			current_state <= next_state;
		end
	end

	always @(current_state or instr)
	begin
		data_sel[1:0] =	2'b00;
		sel_acc =	1'b0;
		sel_cy =	1'b0;
		sel_opa =	1'b0;
		sel_opb[1:0] =	2'b00;
		sel_func =	1'b0;
		sel_ram_adr =	1'b0;
		ram_cen =	1'b1;
		ram_wen =	1'b1;
		ram_oen =	1'b1;
		case (current_state)
		S_READY_FOR_INSTR:
			begin
				data_sel[1:0] =	2'b00;
				sel_acc =	1'b0;
				sel_cy =	1'b0;
				sel_opa =	1'b0;
				sel_opb[1:0] =	2'b00;
				sel_func =	1'b0;

				case (instr)
				I_MOV_IN_TO_ACC:
					begin
						next_state = S_I2A;
					end
				I_ADD_IN_TO_ACC:
					begin
						next_state = S_I2OPA_A2OPB;
					end
				I_SHIFT_ACC:
					begin
						next_state = S_A2OPB;
					end
				I_MOV_IN_TO_ADR:
					begin
						next_state = S_I2ADR;
					end
				I_MOV_IN_TO_RAM:
					begin
						next_state = S_I2RAM;
					end
				I_MOV_RAM_TO_ACC:
					begin
						next_state = S_RAM2A;
					end
				default:
					begin
						next_state = S_READY_FOR_INSTR;
					end
				endcase
			end
		S_I2A:
			begin
				data_sel[1:0] =	2'b00;
				sel_acc =	1'b1;
				sel_cy =	1'b0;
				sel_opa =	1'b0;
				sel_opb[1:0] =	2'b00;
				sel_func =	1'b0;

				next_state = S_READY_FOR_INSTR;
			end
		S_I2OPA_A2OPB:
			begin
				data_sel[1:0] =	2'b00;
				sel_acc =	1'b0;
				sel_cy =	1'b0;
				sel_opa =	1'b1;
				sel_opb[1:0] =	2'b10;
				sel_func =	1'b0;

				next_state = S_ADD_AB2A;
			end
		S_ADD_AB2A:
			begin
				data_sel[1:0] =	2'b10;
				sel_acc =	1'b1;
				sel_cy =	1'b1;
				sel_opa =	1'b0;
				sel_opb[1:0] =	2'b00;
				sel_func =	1'b0;

				next_state = S_READY_FOR_INSTR;
			end
		S_A2OPB:
			begin
				data_sel[1:0] =	2'b00;
				sel_acc =	1'b0;
				sel_cy =	1'b0;
				sel_opa =	1'b0;
				sel_opb[1:0] =	2'b10;
				sel_func =	1'b0;

				next_state = S_SH_OPB2A;
			end
		S_SH_OPB2A:
			begin
				data_sel[1:0] =	2'b10;
				sel_acc =	1'b1;
				sel_cy =	1'b1;
				sel_opa =	1'b0;
				sel_opb[1:0] =	2'b00;
				sel_func =	1'b1;

				next_state = S_READY_FOR_INSTR;
			end
		S_I2ADR:
			begin
				sel_ram_adr =	1'b1;

				next_state = S_READY_FOR_INSTR;
			end
		S_I2RAM:
			begin
				ram_cen =	1'b0;
				ram_wen =	1'b0;

				next_state = S_READY_FOR_INSTR;
			end
		S_RAM2A:
			begin
				ram_cen =	1'b0;

				next_state = S_RAM2AB;
			end
		S_RAM2AB:
			begin
				data_sel[1:0] =	2'b11;
				sel_acc =	1'b1;
				ram_cen =	1'b0;
				ram_oen =	1'b0;

				next_state = S_READY_FOR_INSTR;
			end
		default:
			begin
				data_sel[1:0] =	2'b00;
				sel_acc =	1'b0;
				sel_cy =	1'b0;
				sel_opa =	1'b0;
				sel_opb[1:0] =	2'b00;
				sel_func =	1'b0;

				next_state = S_READY_FOR_INSTR;
			end
		endcase
	end

endmodule