`timescale 1ns/100ps
//_____________________________________________
// Company      :   tud			      	
// Author       :   ander			
// E-Mail   	:   <email>					
//								
// Date         :   Thu Nov  2 12:42:31 2006				
// Last Change  :   Thu Nov  2 12:42:31 2006			
// Module Name  :   output_reg					
// Filename     :   output_reg.v				
// Project Name	:   prz/tutorial06				
// Description	:   <short description>			
//								
//_____________________________________________
module output_reg (
	clk,
	a_reset_l,
	data_bus,
	data_out
);

	input 		clk;
	input 		a_reset_l;
	input [7:0] 	data_bus;
	
	output [7:0]	data_out;
	reg [7:0]	data_out;

	always @ (posedge clk or negedge a_reset_l)
	begin
		if (a_reset_l == 1'b0) begin
			data_out <= 8'h00;
		end
		else begin
			data_out <= data_bus;
		end
	end
		
endmodule