//Radix-2 SRT Verilog Code

module SRT(Dividend,Divisor,Quotient,Remainder);
input [7:0]Dividend;
input [3:0]Divisor;
output [4:0]Quotient;
output [8:0]Remainder;
                                                                                
wire [4:0]q;
wire [4:0]full_divisor;
wire [8:0]r1,r2,r3,r4;
wire encode0,encode1,encode2,encode3;
wire q0,q1,q2,q3;
                                                                                
assign full_divisor = {1'b0,Divisor};
/* remainder correction if Dividend > 0 & remainder < 0*/
assign Remainder = (r4[8]) ? ((r4+{full_divisor,4'b0000}) >> 4 ): (r4>>4);
                                                                                
Divide d1({1'b0,Dividend},full_divisor,encode3,q3,r1);
Divide d2(r1,full_divisor,encode2,q2,r2);
Divide d3(r2,full_divisor,encode1,q1,r3);
Divide d4(r3,full_divisor,encode0,q0,r4);
/* convert q when q is include (-1)  ie. 100(-1) △0111*/                                                                                
assign q =
{1'b0,(q3 ^ encode3),(q2 ^ encode2),(q1 ^ encode1),(q0 ^ encode0)} -
{1'b0,(q3 & encode3),(q2 & encode2),(q1 & encode1),(q0 & encode0)};
/* correct Quotient if remainder < 0, Quotient = q - ulp*/
assign Quotient = (r4[8]) ? (q-1'b1):(q) ;
endmodule



//Radix-2 SRT Verilog Code (conˇt)

module Divide (r_in,d,encode,q,r_out);
input [8:0] r_in;
input [4:0] d;
output [8:0]r_out;
output encode
ortpur q;
                                                                                
reg [8:0] r_out;
reg encode,q;
wire [8:0]double_r_in;
                                                                                
assign double_r_in = r_in<<1;
                                                                                
always @(double_r_in or d) begin
case(double_r_in[8:7])
/* q = 1 encode to 01 and r_out = double_r_in - remainder */
     2'b01 : begin
            r_out <= double_r_in + {((d ^ 5'b11111)+1'b1),4'b0000};
            encode <= 0;
            q <= 1;
            end
    /* q = (-1) encode to 11 and r_out = double_r_in + remainder */
     2'b10 : begin
r_out <= double_r_in + {d,4'b0000};
            encode <= 1;
            q <= 1;
            end
    /* q = 0 encode to 00 and r_out = double_r_in */
     default : begin
            r_out <= double_r_in;
            encode <= 0;
            q <= 0;
            end
   endcase
end
endmodule