--a_gray2bin carry_chain="MANUAL" carry_chain_length=48 device_family="Cyclone" ignore_carry_buffers="OFF" WIDTH=8 bin gray
--VERSION_BEGIN 6.0 cbx_a_gray2bin 2006:02:28:17:43:38:SJ cbx_mgl 2006:05:17:10:06:16:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.



--synthesis_resources = 
SUBDESIGN a_gray2bin_p4b
( 
	bin[7..0]	:	output;
	gray[7..0]	:	input;
) 
VARIABLE 
	xor0	: WIRE;
	xor1	: WIRE;
	xor2	: WIRE;
	xor3	: WIRE;
	xor4	: WIRE;
	xor5	: WIRE;
	xor6	: WIRE;

BEGIN 
	bin[] = ( gray[7..7], xor6, xor5, xor4, xor3, xor2, xor1, xor0);
	xor0 = (gray[0..0] $ xor1);
	xor1 = (gray[1..1] $ xor2);
	xor2 = (gray[2..2] $ xor3);
	xor3 = (gray[3..3] $ xor4);
	xor4 = (gray[4..4] $ xor5);
	xor5 = (gray[5..5] $ xor6);
	xor6 = (gray[7..7] $ gray[6..6]);
END;
--VALID FILE